Hello Giacomo Travaglini, Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/7823
to review the following change.
Change subject: arch-arm: Fault when dc ivac is executed from EL0
......................................................................
arch-arm: Fault when dc ivac is executed from EL0
A previous change enabled execution of dc ivac from EL0 when
SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data
cache maintenance operation by VA that cannot be executed from
EL0. This changeset essential reverts the change:
8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1
Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c
Reviewed-by: Jack Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18..a20c263 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -922,8 +922,7 @@
if (el == EL0 && !sctlr.dze)
return false;
}
- if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
- reg == MISCREG_DC_IVAC_Xt) {
+ if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uci)
return false;
@@ -3557,7 +3556,7 @@
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_IVAC_Xt)
.warnNotFail()
- .writes(1);
+ .writes(1).exceptUserMode();
InitReg(MISCREG_DC_ISW_Xt)
.warnNotFail()
.writes(1).exceptUserMode();
--
To view, visit https://gem5-review.googlesource.com/7823
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c
Gerrit-Change-Number: 7823
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
