Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13997
to review the following change.
Change subject: arch-arm: Refactor ISA::clear by adding a ISA::clear32
method
......................................................................
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
The patch is also moving some initialization code to be used
by AArch64 as well since the registers are mapped to AArch64 ones.
Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 22d275d..a849d04 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -124,38 +124,6 @@
// AArch32 or AArch64
initID64(p);
- miscRegs[MISCREG_ID_ISAR5] = insertBits(
- miscRegs[MISCREG_ID_ISAR5], 19, 4,
- haveCrypto ? 0x1112 : 0x0);
-
- if (FullSystem && system->highestELIs64()) {
- // Initialize AArch64 state
- clear64(p);
- return;
- }
-
- // Initialize AArch32 state...
-
- CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
-
- SCTLR sctlr = 0;
- sctlr.te = (bool) sctlr_rst.te;
- sctlr.nmfi = (bool) sctlr_rst.nmfi;
- sctlr.v = (bool) sctlr_rst.v;
- sctlr.u = 1;
- sctlr.xp = 1;
- sctlr.rao2 = 1;
- sctlr.rao3 = 1;
- sctlr.rao4 = 0xf; // SCTLR[6:3]
- sctlr.uci = 1;
- sctlr.dze = 1;
- miscRegs[MISCREG_SCTLR_NS] = sctlr;
- miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
- miscRegs[MISCREG_HCPTR] = 0;
-
// Start with an event in the mailbox
miscRegs[MISCREG_SEV_MAILBOX] = 1;
@@ -199,6 +167,7 @@
(2 << 4) | // 5:4
(1 << 2) | // 3:2
0; // 1:0
+
miscRegs[MISCREG_NMRR_NS] =
(1 << 30) | // 31:30
(0 << 26) | // 27:26
@@ -216,6 +185,40 @@
(0 << 2) | // 3:2
0; // 1:0
+ if (FullSystem && system->highestELIs64()) {
+ // Initialize AArch64 state
+ clear64(p);
+ return;
+ }
+
+ // Initialize AArch32 state...
+ clear32(p, sctlr_rst);
+}
+
+void
+ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
+{
+ CPSR cpsr = 0;
+ cpsr.mode = MODE_USER;
+
+ miscRegs[MISCREG_CPSR] = cpsr;
+ updateRegMap(cpsr);
+
+ SCTLR sctlr = 0;
+ sctlr.te = (bool) sctlr_rst.te;
+ sctlr.nmfi = (bool) sctlr_rst.nmfi;
+ sctlr.v = (bool) sctlr_rst.v;
+ sctlr.u = 1;
+ sctlr.xp = 1;
+ sctlr.rao2 = 1;
+ sctlr.rao3 = 1;
+ sctlr.rao4 = 0xf; // SCTLR[6:3]
+ sctlr.uci = 1;
+ sctlr.dze = 1;
+ miscRegs[MISCREG_SCTLR_NS] = sctlr;
+ miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
+ miscRegs[MISCREG_HCPTR] = 0;
+
miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_FPSID] = p->fpsid;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 885190c..89c673e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -412,6 +412,7 @@
void clear();
protected:
+ void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
void clear64(const ArmISAParams *p);
void initID32(const ArmISAParams *p);
void initID64(const ArmISAParams *p);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13997
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Gerrit-Change-Number: 13997
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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