Ivan Pizarro has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14555
Change subject: arch-arm: Additional bits in misc ARM registers to use with
the TLB and page walker
......................................................................
arch-arm: Additional bits in misc ARM registers to use with the TLB and
page walker
Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
---
M src/arch/arm/miscregs_types.hh
1 file changed, 16 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index c3ee6ca..940bf39 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -271,6 +271,11 @@
Bitfield<0> vm;
EndBitUnion(HCR)
+ BitUnion32(HCR2)
+ Bitfield<1> id;
+ Bitfield<0> cd;
+ EndBitUnion(HCR2)
+
BitUnion32(NSACR)
Bitfield<20> nstrcdis;
Bitfield<19> rfr;
@@ -319,6 +324,7 @@
// DC CVAC and IC IVAU instructions
// (AArch64 SCTLR_EL1 only)
Bitfield<25> ee; // Exception Endianness
+ Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
Bitfield<24> e0e; // Endianness of explicit data accesses at
EL0
// (AArch64 SCTLR_EL1 only)
Bitfield<23> xp; // Extended page table enable (dropped in
ARMv7)
@@ -460,6 +466,7 @@
Bitfield<5> pd1;
// Long-descriptor translation table format
Bitfield<2, 0> t0sz;
+ Bitfield<6> t2e;
Bitfield<7> epd0;
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
@@ -481,6 +488,8 @@
// TCR_EL2/3 (AArch64)
Bitfield<18, 16> ps;
Bitfield<20> tbi;
+ Bitfield<41> hpd0;
+ Bitfield<42> hpd1;
EndBitUnion(TTBCR)
// Fields of TCR_EL{1,2,3} (mostly overlapping)
@@ -505,6 +514,10 @@
Bitfield<36> as; // EL1
Bitfield<37> tbi0; // EL1
Bitfield<38> tbi1; // EL1
+ Bitfield<39> ha;
+ Bitfield<40> hd;
+ Bitfield<41> hpd0;
+ Bitfield<42> hpd1;
EndBitUnion(TCR)
BitUnion32(HTCR)
@@ -512,6 +525,7 @@
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
Bitfield<13, 12> sh0;
+ Bitfield<24> hpd;
EndBitUnion(HTCR)
BitUnion32(VTCR_t)
@@ -524,6 +538,8 @@
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
Bitfield<18, 16> ps; // Only defined for VTCR_EL2
+ Bitfield<21> ha; // Only defined for VTCR_EL2
+ Bitfield<22> hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
BitUnion32(PRRR)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14555
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Gerrit-Change-Number: 14555
Gerrit-PatchSet: 1
Gerrit-Owner: Ivan Pizarro <ivan.piza...@metempsy.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
