Ivan Pizarro has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/14555 )

Change subject: arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker
......................................................................

arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker

Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Reviewed-on: https://gem5-review.googlesource.com/c/14555
Reviewed-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/miscregs_types.hh
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index c3ee6ca..f668d9b 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -460,6 +460,7 @@
         Bitfield<5> pd1;
         // Long-descriptor translation table format
         Bitfield<2, 0> t0sz;
+        Bitfield<6> t2e;
         Bitfield<7> epd0;
         Bitfield<9, 8> irgn0;
         Bitfield<11, 10> orgn0;
@@ -481,6 +482,8 @@
         // TCR_EL2/3 (AArch64)
         Bitfield<18, 16> ps;
         Bitfield<20> tbi;
+        Bitfield<41> hpd0;
+        Bitfield<42> hpd1;
     EndBitUnion(TTBCR)

     // Fields of TCR_EL{1,2,3} (mostly overlapping)
@@ -505,6 +508,10 @@
         Bitfield<36> as; // EL1
         Bitfield<37> tbi0; // EL1
         Bitfield<38> tbi1; // EL1
+        Bitfield<39> ha;
+        Bitfield<40> hd;
+        Bitfield<41> hpd0;
+        Bitfield<42> hpd1;
     EndBitUnion(TCR)

     BitUnion32(HTCR)
@@ -512,6 +519,7 @@
         Bitfield<9, 8> irgn0;
         Bitfield<11, 10> orgn0;
         Bitfield<13, 12> sh0;
+        Bitfield<24> hpd;
     EndBitUnion(HTCR)

     BitUnion32(VTCR_t)
@@ -524,6 +532,8 @@
         Bitfield<13, 12> sh0;
         Bitfield<15, 14> tg0;
         Bitfield<18, 16> ps; // Only defined for VTCR_EL2
+        Bitfield<21> ha;     // Only defined for VTCR_EL2
+        Bitfield<22> hd;     // Only defined for VTCR_EL2
     EndBitUnion(VTCR_t)

     BitUnion32(PRRR)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Gerrit-Change-Number: 14555
Gerrit-PatchSet: 7
Gerrit-Owner: Ivan Pizarro <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Ivan Pizarro <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: merged
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