Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/10401 )
Change subject: arm: properly handle RES0/1 for SCTLRs
......................................................................
arm: properly handle RES0/1 for SCTLRs
They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.
Also fix this for HVBAR.
Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 58 insertions(+), 14 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 319cc9c..647ecf7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -659,16 +659,6 @@
return readMiscRegNoEffect(MISCREG_DFAR_S);
case MISCREG_HIFAR: // alias for secure IFAR
return readMiscRegNoEffect(MISCREG_IFAR_S);
- case MISCREG_HVBAR: // bottom bits reserved
- return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
- case MISCREG_SCTLR:
- return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
- case MISCREG_SCTLR_EL1:
- return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
- case MISCREG_SCTLR_EL2:
- case MISCREG_SCTLR_EL3:
- case MISCREG_HSCTLR:
- return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
case MISCREG_ID_PFR0:
// !ThumbEE | !Jazelle | Thumb | ARM
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 1eee781..7c1a693 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2453,6 +2453,26 @@
// is running in aarch64 (aarch32EL3 = false)
bool aarch32EL3 = haveSecurity && !highestELIs64;
+ // Set Privileged Access Never on taking an exception to EL1 (Arm
8.1+),
+ // unsupported
+ bool SPAN = false;
+
+ // Implicit error synchronization event enable (Arm 8.2+), unsupported
+ bool IESB = false;
+
+ // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
+ // unsupported
+ bool LSMAOE = false;
+
+ // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
+ bool nTLSMD = false;
+
+ // Pointer authentication (Arm 8.3+), unsupported
+ bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
+ bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
+ bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
+ bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
+
/**
* Some registers alias with others, and therefore need to be
translated.
* When two mapping registers are given, they are the 32b lower and
@@ -2747,7 +2767,13 @@
InitReg(MISCREG_VMPIDR)
.hyp().monNonSecure();
InitReg(MISCREG_SCTLR)
- .banked();
+ .banked()
+ // readMiscRegNoEffect() uses this metadata
+ // despite using children (below) as backing store
+ .res0(0x8d22c600)
+ .res1(0x00400800 | (SPAN ? 0 : 0x800000)
+ | (LSMAOE ? 0 : 0x10)
+ | (nTLSMD ? 0 : 0x8));
InitReg(MISCREG_SCTLR_NS)
.bankedChild()
.privSecure(!aarch32EL3)
@@ -2775,7 +2801,13 @@
InitReg(MISCREG_NSACR)
.allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
InitReg(MISCREG_HSCTLR)
- .hyp().monNonSecure();
+ .hyp().monNonSecure()
+ .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
+ | (IESB ? 0 : 0x200000)
+ | (EnDA ? 0 : 0x8000000)
+ | (EnIB ? 0 : 0x40000000)
+ | (EnIA ? 0 : 0x80000000))
+ .res1(0x30c50830);
InitReg(MISCREG_HACTLR)
.hyp().monNonSecure();
InitReg(MISCREG_HCR)
@@ -3175,7 +3207,8 @@
InitReg(MISCREG_ISR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_HVBAR)
- .hyp().monNonSecure();
+ .hyp().monNonSecure()
+ .res0(0x1f);
InitReg(MISCREG_FCSEIDR)
.unimplemented()
.warnNotFail()
@@ -3537,6 +3570,14 @@
.mapsTo(MISCREG_VMPIDR);
InitReg(MISCREG_SCTLR_EL1)
.allPrivileges().exceptUserMode()
+ .res0( 0x20440 | (EnDB ? 0 : 0x2000)
+ | (IESB ? 0 : 0x200000)
+ | (EnDA ? 0 : 0x8000000)
+ | (EnIB ? 0 : 0x40000000)
+ | (EnIA ? 0 : 0x80000000))
+ .res1(0x500800 | (SPAN ? 0 : 0x800000)
+ | (nTLSMD ? 0 : 0x8000000)
+ | (LSMAOE ? 0 : 0x10000000))
.mapsTo(MISCREG_SCTLR_NS);
InitReg(MISCREG_ACTLR_EL1)
.allPrivileges().exceptUserMode()
@@ -3546,6 +3587,12 @@
.mapsTo(MISCREG_CPACR);
InitReg(MISCREG_SCTLR_EL2)
.hyp().mon()
+ .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
+ | (IESB ? 0 : 0x200000)
+ | (EnDA ? 0 : 0x8000000)
+ | (EnIB ? 0 : 0x40000000)
+ | (EnIA ? 0 : 0x80000000))
+ .res1(0x30c50830)
.mapsTo(MISCREG_HSCTLR);
InitReg(MISCREG_ACTLR_EL2)
.hyp().mon()
@@ -3566,7 +3613,13 @@
.hyp().mon()
.mapsTo(MISCREG_HACR);
InitReg(MISCREG_SCTLR_EL3)
- .mon();
+ .mon()
+ .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
+ | (IESB ? 0 : 0x200000)
+ | (EnDA ? 0 : 0x8000000)
+ | (EnIB ? 0 : 0x40000000)
+ | (EnIA ? 0 : 0x80000000))
+ .res1(0x30c50830);
InitReg(MISCREG_ACTLR_EL3)
.mon();
InitReg(MISCREG_SCR_EL3)
@@ -3892,6 +3945,7 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_VBAR_EL2)
.hyp().mon()
+ .res0(0x7ff)
.mapsTo(MISCREG_HVBAR);
InitReg(MISCREG_RVBAR_EL2)
.mon().hyp().writes(0);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Gerrit-Change-Number: 10401
Gerrit-PatchSet: 4
Gerrit-Owner: Curtis Dunham <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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