Hello Anouk Van Laer, Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/15275
to review the following change.
Change subject: dev-arm: Added unimplemented GICv2 GICC_DIR
......................................................................
dev-arm: Added unimplemented GICv2 GICC_DIR
This GICC CPU register is not implemented but just gives a warning.
Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-by: Anouk Van Laer <[email protected]>
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 293c72f..1e58718 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -622,6 +622,9 @@
case GICC_APR3:
warn("GIC APRn write ignored because not implemented: %#x\n",
daddr);
break;
+ case GICC_DIR:
+ warn("GIC DIR write ignored because not implemented: %#x\n",
daddr);
+ break;
default:
panic("Tried to write Gic cpu at offset %#x\n", daddr);
break;
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4afad89..49465ad 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -110,6 +110,7 @@
GICC_APR2 = 0xd8, // active priority register 2
GICC_APR3 = 0xdc, // active priority register 3
GICC_IIDR = 0xfc, // cpu interface id register
+ GICC_DIR = 0x1000, // deactive interrupt register
};
static const int SGI_MAX = 16; // Number of Software Gen Interrupts
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Gerrit-Change-Number: 15275
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Anouk Van Laer <[email protected]>
Gerrit-MessageType: newchange
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