Alec Roelke has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16988 )
Change subject: arch-riscv: Implement MHARTID CSR
......................................................................
arch-riscv: Implement MHARTID CSR
This patch implements the MHARTID CSR by intercepting attempts to access
it, similar to the way accesses to the performance counters are
intercepted, to return the thread's context ID.
Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988
Reviewed-by: Alec Roelke <alec.roe...@gmail.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Alec Roelke <alec.roe...@gmail.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/riscv/isa.cc
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Alec Roelke: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d55..cc86752 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
+ case MISCREG_HARTID:
+ return tc->contextId();
case MISCREG_CYCLE:
if (hpmCounterEnabled(MISCREG_CYCLE)) {
DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Gerrit-Change-Number: 16988
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke <alec.roe...@gmail.com>
Gerrit-Reviewer: Alec Roelke <alec.roe...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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