[gem5-dev] Change in gem5/gem5[master]: cpu: Mark ExecContext::tcBase() as const

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24523 )

Change subject: cpu: Mark ExecContext::tcBase() as const
......................................................................

cpu: Mark ExecContext::tcBase() as const

Change-Id: Ia3965c05a1b00e0a9738ddbccb4dc0b651f78e5e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/simple/exec_context.hh
5 files changed, 10 insertions(+), 10 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 85ad544..81b3999 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2013, 2016-2019 ARM Limited
+ * Copyright (c) 2011, 2013, 2016-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -919,7 +919,7 @@
     void setThreadState(ImplState *state) { thread = state; }

     /** Returns the thread context. */
-    ThreadContext *tcBase() { return thread->getTC(); }
+    ThreadContext *tcBase() const { return thread->getTC(); }

   public:
     /** Returns whether or not the eff. addr. source registers are ready.  
*/
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 775381c..7d3d339 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2016-2018 ARM Limited
+ * Copyright (c) 2011, 2016-2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -595,7 +595,7 @@

     void dumpAndExit();

-    ThreadContext *tcBase() override { return tc; }
+    ThreadContext *tcBase() const override { return tc; }
     SimpleThread *threadBase() { return thread; }

     InstResult unverifiedResult;
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index a96ccfc..c1af767 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2018 ARM Limited
+ * Copyright (c) 2014, 2016-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -311,7 +311,7 @@
     /** @} */

     /** Returns a pointer to the ThreadContext. */
-    virtual ThreadContext *tcBase() = 0;
+    virtual ThreadContext *tcBase() const = 0;

     /**
      * @{
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4cc41c6..3e925586 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -393,7 +393,7 @@
         thread.syscall(fault);
     }

-    ThreadContext *tcBase() override { return thread.getTC(); }
+    ThreadContext *tcBase() const override { return thread.getTC(); }

     /* @todo, should make stCondFailures persistent somewhere */
     unsigned int readStCondFailures() const override { return 0; }
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 04be1a0..5924ada 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018 ARM Limited
+ * Copyright (c) 2014-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -505,7 +505,7 @@
     }

     /** Returns a pointer to the ThreadContext. */
-    ThreadContext *tcBase() override { return thread->getTC(); }
+    ThreadContext *tcBase() const override { return thread->getTC(); }

     bool
     readPredicate() const override

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia3965c05a1b00e0a9738ddbccb4dc0b651f78e5e
Gerrit-Change-Number: 24523
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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