Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25651 )
Change subject: arch-riscv: ignore writes to SXL/UXL fields in status
register.
......................................................................
arch-riscv: ignore writes to SXL/UXL fields in status register.
We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.
Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
---
M src/arch/riscv/isa.cc
1 file changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index cfdea22..5c1af29 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -352,6 +352,15 @@
setMiscRegNoEffect(misc_reg, new_val);
}
break;
+ case MISCREG_STATUS:
+ {
+ // these bits are hard-wired
+ RegVal cur = readMiscRegNoEffect(misc_reg);
+ val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
+ val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
+ setMiscRegNoEffect(misc_reg, val);
+ }
+ break;
default:
setMiscRegNoEffect(misc_reg, val);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Gerrit-Change-Number: 25651
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen <nils.asmus...@barkhauseninstitut.org>
Gerrit-MessageType: newchange
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