Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25658 )
Change subject: arch-riscv: respect IALIGN, influenced by toggling 'c'
extension.
......................................................................
arch-riscv: respect IALIGN, influenced by toggling 'c' extension.
According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.
Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.
Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
---
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
2 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 5c1af29..9c5e302 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -288,6 +288,18 @@
tc->getCpuPtr()->getInterruptController(tc->threadId()));
return ic->readIE();
}
+ case MISCREG_SEPC:
+ case MISCREG_MEPC:
+ {
+ auto misa = readMiscRegNoEffect(MISCREG_ISA);
+ RegVal val = readMiscRegNoEffect(misc_reg);
+ // epc[0] is always 0
+ val &= ~static_cast<Addr>(0x1);
+ // if compressed instructions are disabled, epc[1] is set to 0
+ if ((misa & ISA_EXT_C_MASK) == 0)
+ val &= ~static_cast<Addr>(0x2);
+ return val;
+ }
default:
// Try reading HPM counters
// As a placeholder, all HPM counters are just cycle counters
@@ -352,6 +364,17 @@
setMiscRegNoEffect(misc_reg, new_val);
}
break;
+ case MISCREG_ISA:
+ {
+ auto cur_val = readMiscRegNoEffect(misc_reg);
+ // only allow to disable compressed instructions
+ // if the following instruction is 4-byte aligned
+ if ((val & ISA_EXT_C_MASK) == 0 &&
+ (tc->pcState().npc() & 0x3) != 0)
+ val |= cur_val & ISA_EXT_C_MASK;
+ setMiscRegNoEffect(misc_reg, val);
+ }
+ break;
case MISCREG_STATUS:
{
// these bits are hard-wired
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index d5c05a2..9b899e3 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -2,6 +2,7 @@
* Copyright (c) 2013 ARM Limited
* Copyright (c) 2014-2015 Sven Karlsson
* Copyright (c) 2019 Yifei Liu
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -646,6 +647,7 @@
const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
const RegVal ISA_EXT_MASK = mask(26);
+const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Gerrit-Change-Number: 25658
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen <nils.asmus...@barkhauseninstitut.org>
Gerrit-MessageType: newchange
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