Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25012 )
Change subject: scons,arch: Remove simple scalar compatibility.
......................................................................
scons,arch: Remove simple scalar compatibility.
This was primarily in Alpha where disassmbly output could be compatible
(default off, probably not usd in a long time), and floating point
could be compatible (default on). A small bit had crept into x86 from
long ago which is also removed.
Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25012
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M SConstruct
M build_opts/ALPHA
M build_opts/ALPHA_MESI_Two_Level
M build_opts/ALPHA_MOESI_CMP_directory
M build_opts/ALPHA_MOESI_CMP_token
M build_opts/ALPHA_MOESI_hammer
M build_opts/Garnet_standalone
M src/arch/alpha/isa/branch.isa
M src/arch/alpha/isa/decoder.isa
M src/arch/alpha/isa/fp.isa
M src/arch/alpha/isa/main.isa
M src/arch/alpha/isa/pal.isa
M src/arch/alpha/isa/unimp.isa
M src/arch/x86/isa/formats/unimp.isa
14 files changed, 3 insertions(+), 70 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index eb3a9e4..d8158fa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -971,9 +971,6 @@
sorted(CpuModel.dict.keys())),
BoolVariable('EFENCE', 'Link with Electric Fence malloc debugger',
False),
- BoolVariable('SS_COMPATIBLE_FP',
- 'Make floating-point results compatible with
SimpleScalar',
- False),
BoolVariable('USE_SSE2',
'Compile for SSE2 (-msse2) to get IEEE FP on x86 hosts',
False),
@@ -998,9 +995,9 @@
)
# These variables get exported to #defines in config/*.hh (see
src/SConscript).
-export_vars +=
['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA',
- 'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP',
- 'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_VALGRIND',
+export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA', 'CP_ANNOTATE',
+ 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP', 'PROTOCOL',
+ 'HAVE_PROTOBUF', 'HAVE_VALGRIND',
'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG',
'NUMBER_BITS_PER_SET', 'USE_HDF5']
diff --git a/build_opts/ALPHA b/build_opts/ALPHA
index d1f82ce..f4e8ae3 100644
--- a/build_opts/ALPHA
+++ b/build_opts/ALPHA
@@ -1,4 +1,3 @@
TARGET_ISA = 'alpha'
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MI_example'
diff --git a/build_opts/ALPHA_MESI_Two_Level
b/build_opts/ALPHA_MESI_Two_Level
index 123b85d..89b0e1b 100644
--- a/build_opts/ALPHA_MESI_Two_Level
+++ b/build_opts/ALPHA_MESI_Two_Level
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MESI_Two_Level'
diff --git a/build_opts/ALPHA_MOESI_CMP_directory
b/build_opts/ALPHA_MOESI_CMP_directory
index 816453e..ef00ae1 100644
--- a/build_opts/ALPHA_MOESI_CMP_directory
+++ b/build_opts/ALPHA_MOESI_CMP_directory
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_directory'
diff --git a/build_opts/ALPHA_MOESI_CMP_token
b/build_opts/ALPHA_MOESI_CMP_token
index 3851c51..d3a97ed 100644
--- a/build_opts/ALPHA_MOESI_CMP_token
+++ b/build_opts/ALPHA_MOESI_CMP_token
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_token'
diff --git a/build_opts/ALPHA_MOESI_hammer b/build_opts/ALPHA_MOESI_hammer
index 4639cac..91e01d6 100644
--- a/build_opts/ALPHA_MOESI_hammer
+++ b/build_opts/ALPHA_MOESI_hammer
@@ -1,3 +1,2 @@
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_hammer'
diff --git a/build_opts/Garnet_standalone b/build_opts/Garnet_standalone
index 46ae29a..df97b5b 100644
--- a/build_opts/Garnet_standalone
+++ b/build_opts/Garnet_standalone
@@ -1,4 +1,3 @@
TARGET_ISA = 'alpha'
-SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'Garnet_standalone'
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index 8f641a4..3641861 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -175,13 +175,6 @@
ss << ",";
}
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- if (_numSrcRegs == 0 && _numDestRegs == 0) {
- printReg(ss, 31);
- ss << ",";
- }
-#endif
-
Addr target = pc + 4 + disp;
std::string str;
@@ -200,13 +193,6 @@
ccprintf(ss, "%-10s ", mnemonic);
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- if (_numDestRegs == 0) {
- printReg(ss, 31);
- ss << ",";
- }
-#endif
-
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
ss << ",";
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index abf6fb2..a61db0b 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -600,19 +600,11 @@
0xb: decode FA {
31: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#if SS_COMPATIBLE_FP
- 0x0b: sqrts({{
- if (Fb < 0.0)
- fault = std::make_shared<ArithmeticFault>();
- Fc = sqrt(Fb);
- }}, FloatSqrtOp);
-#else
0x0b: sqrts({{
if (Fb_sf < 0.0)
fault = std::make_shared<ArithmeticFault>();
Fc_sf = sqrt(Fb_sf);
}}, FloatSqrtOp);
-#endif
0x2b: sqrtt({{
if (Fb < 0.0)
fault = std::make_shared<ArithmeticFault>();
@@ -644,17 +636,10 @@
// check for valid trapping modes here
0,1,5,7: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#if SS_COMPATIBLE_FP
- 0x00: adds({{ Fc = Fa + Fb; }});
- 0x01: subs({{ Fc = Fa - Fb; }});
- 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
- 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
-#else
0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }},
FloatMultOp);
0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }},
FloatDivOp);
-#endif
0x20: addt({{ Fc = Fa + Fb; }});
0x21: subt({{ Fc = Fa - Fb; }});
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 6e03f46..99d13ac 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -150,7 +150,6 @@
{
std::string mnem_str(mnemonic);
-#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
suffix += ((_destRegIdx[0].isFloatReg())
? fpTrappingModeSuffix[trappingMode]
@@ -160,7 +159,6 @@
if (suffix != "") {
mnem_str = csprintf("%s/%s", mnemonic, suffix);
}
-#endif
std::stringstream ss;
ccprintf(ss, "%-10s ", mnem_str.c_str());
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 3f7e1a3..ab145eb 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -47,7 +47,6 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/types.hh"
-#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh" // some constructors use MemReq flags
@@ -64,7 +63,6 @@
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
-#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
#include "sim/full_system.hh"
@@ -83,7 +81,6 @@
#include "arch/generic/memhelpers.hh"
#include "base/cp_annotate.hh"
#include "base/fenv.hh"
-#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "mem/packet.hh"
@@ -215,10 +212,6 @@
//
output header {{
-// uncomment the following to get SimpleScalar-compatible disassembly
-// (useful for diffing output traces).
-// #define SS_COMPATIBLE_DISASSEMBLY
-
/**
* Base class for all Alpha static instructions.
*/
@@ -409,11 +402,7 @@
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return originalDisassembly;
-#else
return csprintf("%-10s (%s)", "nop", originalDisassembly);
-#endif
}
}};
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 69b8a47..f48cbfe 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -59,11 +59,7 @@
EmulatedCallPal::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return csprintf("%s %s", "call_pal", mnemonic);
-#else
return csprintf("%-10s %s", "call_pal", mnemonic);
-#endif
}
}};
@@ -179,9 +175,6 @@
std::string
HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
-#else
// HW_LDST_LOCK and HW_LDST_COND are the same bit.
const char *lock_str =
(HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
@@ -193,7 +186,6 @@
HW_LDST_QUAD ? ",QUAD" : "",
HW_LDST_VPTE ? ",VPTE" : "",
lock_str);
-#endif
}
}};
diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index e5a773d..011a90c 100644
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -103,11 +103,7 @@
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return csprintf("%-10s", mnemonic);
-#else
return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
}
}};
diff --git a/src/arch/x86/isa/formats/unimp.isa
b/src/arch/x86/isa/formats/unimp.isa
index 963e07c..807e40a 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -112,11 +112,7 @@
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return csprintf("%-10s", mnemonic);
-#else
return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
}
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704
Gerrit-Change-Number: 25012
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Steve Reinhardt <ste...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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