Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32316 )
Change subject: systemc,sim: Update port terminology
......................................................................
systemc,sim: Update port terminology
Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
---
M src/sim/System.py
M src/sim/system.hh
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/sim/System.py b/src/sim/System.py
index e028f48..dcef74b 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -51,7 +51,7 @@
class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
- system_port = MasterPort("System port")
+ system_port = RequestPort("System port")
cxx_exports = [
PyBindMethod("getMemoryMode"),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821..8e2c472 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -79,7 +79,7 @@
* master for debug access and for non-structural entities that do
* not have a port of their own.
*/
- class SystemPort : public MasterPort
+ class SystemPort : public RequestPort
{
public:
@@ -87,7 +87,7 @@
* Create a system port with a name and an owner.
*/
SystemPort(const std::string &_name, SimObject *_owner)
- : MasterPort(_name, _owner)
+ : RequestPort(_name, _owner)
{ }
bool recvTimingResp(PacketPtr pkt) override
{ panic("SystemPort does not receive timing!\n"); return false; }
@@ -237,7 +237,7 @@
*
* @return a reference to the system port we own
*/
- MasterPort& getSystemPort() { return _systemPort; }
+ RequestPort& getSystemPort() { return _systemPort; }
/**
* Additional function to return the Port of a memory object.
diff --git a/src/systemc/tlm_bridge/TlmBridge.py
b/src/systemc/tlm_bridge/TlmBridge.py
index 6218153..1851464 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -37,7 +37,7 @@
system = Param.System(Parent.any, "system")
- gem5 = SlavePort('gem5 slave port')
+ gem5 = ResponsePort('gem5 slave port')
addr_ranges = VectorParam.AddrRange([],
'Addresses served by this port\'s TLM side')
@@ -49,7 +49,7 @@
system = Param.System(Parent.any, "system")
- gem5 = MasterPort('gem5 master port')
+ gem5 = RequestPort('gem5 master port')
class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh
b/src/systemc/tlm_bridge/gem5_to_tlm.hh
index afc8ad9..7e69e3c 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -85,7 +85,7 @@
class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
{
private:
- class BridgeSlavePort : public SlavePort
+ class BridgeSlavePort : public ResponsePort
{
protected:
Gem5ToTlmBridge<BITWIDTH> &bridge;
@@ -130,7 +130,7 @@
public:
BridgeSlavePort(const std::string &name_,
Gem5ToTlmBridge<BITWIDTH> &bridge_) :
- SlavePort(name_, nullptr), bridge(bridge_)
+ ResponsePort(name_, nullptr), bridge(bridge_)
{}
};
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh
b/src/systemc/tlm_bridge/tlm_to_gem5.hh
index 03bac29..e2e7540 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -89,7 +89,7 @@
TlmSenderState(tlm::tlm_generic_payload &trans) : trans(trans) {}
};
- class BridgeMasterPort : public MasterPort
+ class BridgeMasterPort : public RequestPort
{
protected:
TlmToGem5Bridge<BITWIDTH> &bridge;
@@ -105,7 +105,7 @@
public:
BridgeMasterPort(const std::string &name_,
TlmToGem5Bridge<BITWIDTH> &bridge_) :
- MasterPort(name_, nullptr), bridge(bridge_)
+ RequestPort(name_, nullptr), bridge(bridge_)
{}
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Gerrit-Change-Number: 32316
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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