Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33519 )
Change subject: arch: Update master/slave variables
......................................................................
arch: Update master/slave variables
Change-Id: Ib2ddf64ff250b1c78ed2d950850058048ddfdc9d
---
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b25e8a7..7767c80 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -288,12 +288,12 @@
void
X86ISA::Interrupts::init()
{
- panic_if(!intMasterPort.isConnected(),
+ panic_if(!intRequestPort.isConnected(),
"Int port not connected to anything!");
panic_if(!pioPort.isConnected(),
"Pio port of %s not connected to anything!", name());
- intSlavePort.sendRangeChange();
+ intResponsePort.sendRangeChange();
pioPort.sendRangeChange();
}
@@ -541,7 +541,7 @@
regs[APIC_INTERRUPT_COMMAND_LOW] = low;
for (auto id: apics) {
PacketPtr pkt = buildIntTriggerPacket(id, message);
- intMasterPort.sendMessage(pkt, sys->isTimingMode(),
+ intRequestPort.sendMessage(pkt, sys->isTimingMode(),
[this](PacketPtr pkt) { completeIPI(pkt); });
}
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
@@ -603,8 +603,8 @@
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0),
- intSlavePort(name() + ".int_responder", this, this),
- intMasterPort(name() + ".int_requestor", this, this, p->int_latency),
+ intResponsePort(name() + ".int_responder", this, this),
+ intRequestPort(name() + ".int_requestor", this, this,
p->int_latency),
pioPort(this), pioDelay(p->pio_latency)
{
memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 1a4904f..8712bbc 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -174,8 +174,8 @@
int initialApicId;
// Ports for interrupts.
- IntSlavePort<Interrupts> intSlavePort;
- IntMasterPort<Interrupts> intMasterPort;
+ IntSlavePort<Interrupts> intResponsePort;
+ IntMasterPort<Interrupts> intRequestPort;
// Port for memory mapped register accesses.
PioPort<Interrupts> pioPort;
@@ -231,7 +231,7 @@
if (if_name == "int_requestor") {
return intRequestPort;
} else if (if_name == "int_responder") {
- return intSlavePort;
+ return intResponsePort;
} else if (if_name == "pio") {
return pioPort;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2ddf64ff250b1c78ed2d950850058048ddfdc9d
Gerrit-Change-Number: 33519
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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