Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33517 )
Change subject: cpu: Replaced master/slave variables and comments
......................................................................
cpu: Replaced master/slave variables and comments
Change-Id: I99bca2ae43b39a8f8243b2a4af0a2eb6e941a2af
---
M src/cpu/o3/commit_impl.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/traffic_gen.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
6 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index de79206..a549bf1 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -733,7 +733,7 @@
{
// Verify that we still have an interrupt to handle
if (!cpu->checkInterrupts(0)) {
- DPRINTF(Commit, "Pending interrupt is cleared by master before "
+ DPRINTF(Commit, "Pending interrupt is cleared by requestor before "
"it got handled. Restart fetching from the orig path.\n");
toIEW->commitInfo[0].clearInterrupt = true;
interrupt = NoFault;
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index ff50a19..f56d7c9 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -44,7 +44,7 @@
# generated (Random, Linear, Trace etc)
class StreamGenType(ScopedEnum): vals = [ 'none', 'fixed', 'random' ]
-# The traffic generator is a master module that generates stimuli for
+# The traffic generator is a requestor module that generates stimuli for
# the memory system, based on a collection of simple behaviours that
# are either probabilistic or based on traces. It can be used stand
# alone for creating test cases for interconnect and memory
@@ -57,7 +57,7 @@
cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
# Port used for sending requests and receiving responses
- port = RequestPort("Master port")
+ port = RequestPort("This port sends requests and receives responses")
# System used to determine the mode of the memory system
system = Param.System(Parent.any, "System this generator is part of")
@@ -110,9 +110,9 @@
def connectCachedPorts(self, bus):
if hasattr(self, '_cached_ports') and (len(self._cached_ports) >
0):
for p in self._cached_ports:
- exec('self.%s = bus.slave' % p)
+ exec('self.%s = bus.cpu_side' % p)
else:
- self.port = bus.slave
+ self.port = bus.cpu_side
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 17b1aa1..2466206 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -53,7 +53,7 @@
struct BaseTrafficGenParams;
/**
- * The traffic generator is a master module that generates stimuli for
+ * The traffic generator is a memside module that generates stimuli for
* the memory system, based on a collection of simple generator
* behaviours that are either probabilistic or based on traces. It can
* be used stand alone for creating test cases for interconnect and
@@ -123,7 +123,7 @@
const int maxOutstandingReqs;
- /** Master port specialisation for the traffic generator */
+ /** Request port specialisation for the traffic generator */
class TrafficGenPort : public RequestPort
{
public:
@@ -157,7 +157,7 @@
*/
void update();
- /** The instance of master port used by the traffic generator. */
+ /** The instance of request port used by the traffic generator. */
TrafficGenPort port;
/** Packet waiting to be sent. */
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh
b/src/cpu/testers/traffic_gen/traffic_gen.hh
index 3f1c2ab..5dab256 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -45,7 +45,7 @@
struct TrafficGenParams;
/**
- * The traffic generator is a master module that generates stimuli for
+ * The traffic generator is a memside module that generates stimuli for
* the memory system, based on a collection of simple behaviours that
* are either probabilistic or based on traces. It can be used stand
* alone for creating test cases for interconnect and memory
@@ -53,7 +53,7 @@
* components that are not yet modelled in detail, e.g. a video engine
* or baseband subsystem in an SoC.
*
- * The traffic generator has a single master port that is used to send
+ * The traffic generator has a single request port that is used to send
* requests, independent of the specific behaviour. The behaviour of
* the traffic generator is specified in a configuration file, and this
* file describes a state transition graph where each state is a
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index dd91257..664b1fe 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -46,12 +46,12 @@
: BaseCPU(params),
icachePort(this),
dcachePort(this),
- instMasterID(params->system->getMasterId(this, "inst")),
- dataMasterID(params->system->getMasterId(this, "data")),
+ instUniqueID(params->system->getMasterId(this, "inst")),
+ dataUniqueID(params->system->getMasterId(this, "data")),
instTraceFile(params->instTraceFile),
dataTraceFile(params->dataTraceFile),
- icacheGen(*this, ".iside", icachePort, instMasterID,
instTraceFile),
- dcacheGen(*this, ".dside", dcachePort, dataMasterID, dataTraceFile,
+ icacheGen(*this, ".iside", icachePort, instUniqueID,
instTraceFile),
+ dcacheGen(*this, ".dside", dcachePort, dataUniqueID, dataTraceFile,
params),
icacheNextEvent([this]{ schedIcacheNext(); }, name()),
dcacheNextEvent([this]{ schedDcacheNext(); }, name()),
@@ -673,7 +673,7 @@
}
pkt->dataDynamic(pkt_data);
- // Call MasterPort method to send a timing request for this packet
+ // Call RequestPort method to send a timing request for this packet
bool success = port.sendTimingReq(pkt);
++numSendAttempted;
@@ -1162,7 +1162,7 @@
memset(pkt_data, 0xA, req->getSize());
}
- // Call MasterPort method to send a timing request for this packet
+ // Call RequestPort method to send a timing request for this packet
bool success = port.sendTimingReq(pkt);
if (!success) {
// If it fails, save the packet to retry when a retry is signalled
by
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index cd292fb..9ace810 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -65,7 +65,7 @@
* same trace is used for playback on different memory sub-systems.
*
* The TraceCPU inherits from BaseCPU so some virtual methods need to be
- * defined. It has two port subclasses inherited from MasterPort for
+ * defined. It has two port subclasses inherited from RequestPort for
* instruction and data ports. It issues the memory requests deducing the
* timing from the trace and without performing real execution of
micro-ops. As
* soon as the last dependency for an instruction is complete, its
@@ -321,11 +321,11 @@
/** Port to connect to L1 data cache. */
DcachePort dcachePort;
- /** Master id for instruction read requests. */
- const MasterID instMasterID;
+ /** Unique id for instruction read requests. */
+ const MasterID instUniqueID;
- /** Master id for data read and write requests. */
- const MasterID dataMasterID;
+ /** Unique id for data read and write requests. */
+ const MasterID dataUniqueID;
/** File names for input instruction and data traces. */
std::string instTraceFile, dataTraceFile;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I99bca2ae43b39a8f8243b2a4af0a2eb6e941a2af
Gerrit-Change-Number: 33517
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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