Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35821 )
Change subject: WIP dynamic index arrays
......................................................................
WIP dynamic index arrays
Change-Id: I1f9d85c4ddc6fd46084f409592fb5f5bce480ce9
---
M src/arch/SConscript
M src/arch/arm/registers.hh
M src/arch/isa_parser/isa_parser.py
M src/arch/isa_parser/operands.py
M src/arch/mips/isa/base.isa
M src/arch/mips/isa/formats/branch.isa
M src/arch/mips/isa/formats/dsp.isa
M src/arch/mips/isa/formats/fp.isa
M src/arch/mips/isa/formats/int.isa
M src/arch/mips/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/insts/branch.cc
M src/arch/sparc/insts/integer.cc
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/insts/static_inst.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/static_inst.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
27 files changed, 108 insertions(+), 205 deletions(-)
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 5fb543e..273fd3e 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -186,8 +186,6 @@
add_gen('exec-g.cc.inc')
add_gen('exec-ns.cc.inc')
- add_gen('max_inst_regs.hh')
-
# These generated files are also top level sources.
def source_gen(name):
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 630a145..7751db6 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -42,7 +42,6 @@
#define __ARCH_ARM_REGISTERS_HH__
#include "arch/arm/ccregs.hh"
-#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
@@ -52,13 +51,6 @@
namespace ArmISA {
-// For a predicated instruction, we need all the
-// destination registers to also be sources
-const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
- ArmISAInst::MaxInstSrcRegs;
-using ArmISAInst::MaxInstDestRegs;
-using ArmISAInst::MaxMiscDestRegs;
-
// Number of VecElem per Vector Register considering only pre-SVE
// Advanced SIMD registers.
constexpr unsigned NumVecElemPerNeonVecReg = 4;
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index 80d50b7..b80ec09 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -47,6 +47,7 @@
from . import operands
from m5.util.grammar import Grammar
+from .bitfields import *
from .operand_list import *
from .util import *
@@ -281,47 +282,6 @@
#####################################################################
#
-# Bitfield Operator Support
-#
-#####################################################################
-
-bitOp1ArgRE = re.compile(r'<\s*(\w+)\s*:\s*>')
-
-bitOpWordRE = re.compile(r'(?<![\w\.])([\w\.]+)<\s*(\w+)\s*:\s*(\w+)\s*>')
-bitOpExprRE = re.compile(r'\)<\s*(\w+)\s*:\s*(\w+)\s*>')
-
-def substBitOps(code):
- # first convert single-bit selectors to two-index form
- # i.e., <n> --> <n:n>
- code = bitOp1ArgRE.sub(r'<\1:\1>', code)
- # simple case: selector applied to ID (name)
- # i.e., foo<a:b> --> bits(foo, a, b)
- code = bitOpWordRE.sub(r'bits(\1, \2, \3)', code)
- # if selector is applied to expression (ending in ')'),
- # we need to search backward for matching '('
- match = bitOpExprRE.search(code)
- while match:
- exprEnd = match.start()
- here = exprEnd - 1
- nestLevel = 1
- while nestLevel > 0:
- if code[here] == '(':
- nestLevel -= 1
- elif code[here] == ')':
- nestLevel += 1
- here -= 1
- if here < 0:
- sys.exit("Didn't find '('!")
- exprStart = here+1
- newExpr = r'bits(%s, %s, %s)' % (code[exprStart:exprEnd+1],
- match.group(1), match.group(2))
- code = code[:exprStart] + newExpr + code[match.end():]
- match = bitOpExprRE.search(code)
- return code
-
-
-#####################################################################
-#
# Code Parser
#
# The remaining code is the support for automatically extracting
@@ -380,8 +340,7 @@
# The header of the constructor declares the variables to be used
# in the body of the constructor.
header = ''
- header += '\n\t_numSrcRegs = 0;'
- header += '\n\t_numDestRegs = 0;'
+ header += '\n\t_numMiscDestRegs = 0;'
header += '\n\t_numFPDestRegs = 0;'
header += '\n\t_numVecDestRegs = 0;'
header += '\n\t_numVecElemDestRegs = 0;'
@@ -640,13 +599,6 @@
print('#include "%s"' % fn, file=f)
print('}', file=f)
- # max_inst_regs.hh
- self.update('max_inst_regs.hh',
- '''namespace %(namespace)s {
- const int MaxInstSrcRegs = %(maxInstSrcRegs)d;
- const int MaxInstDestRegs = %(maxInstDestRegs)d;
- const int MaxMiscDestRegs = %(maxMiscDestRegs)d;\n}\n''' % self)
-
scaremonger_template ='''// DO NOT EDIT
// This file was automatically generated from an ISA description:
// %(filename)s
diff --git a/src/arch/isa_parser/operands.py
b/src/arch/isa_parser/operands.py
index 6efb868..46241e2 100755
--- a/src/arch/isa_parser/operands.py
+++ b/src/arch/isa_parser/operands.py
@@ -52,8 +52,8 @@
abstract = True
- src_reg_constructor = '\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s);'
- dst_reg_constructor = '\n\t_destRegIdx[_numDestRegs++] =
RegId(%s, %s);'
+ src_reg_constructor = '\n\t_srcRegIdx.push_back(RegId(%s, %s));'
+ dst_reg_constructor = '\n\t_destRegIdx.push_back(RegId(%s, %s));'
def buildReadCode(self, func = None):
subst_dict = {"name": self.base_name,
@@ -483,11 +483,11 @@
numAccessNeeded = 1
if self.is_src:
- c_src = ('\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s, %s);' %
+ c_src = ('\n\t_srcRegIdx.push_back(RegId(%s, %s, %s));' %
(self.reg_class, self.reg_spec, self.elem_spec))
if self.is_dest:
- c_dest = ('\n\t_destRegIdx[_numDestRegs++] =
RegId(%s, %s, %s);' %
+ c_dest = ('\n\t_destRegIdx.push_back(RegId(%s, %s, %s));' %
(self.reg_class, self.reg_spec, self.elem_spec))
c_dest += '\n\t_numVecElemDestRegs++;'
return c_src + c_dest
@@ -686,6 +686,7 @@
if self.is_dest:
c_dest = self.dst_reg_constructor % (self.reg_class,
self.reg_spec)
+ c_dest += '\n\t_numMiscDestRegs++;'
return c_src + c_dest
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 0d51467..feb3bd7 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -97,16 +97,16 @@
// this info. Maybe add bool variable to
// class?
if (strcmp(mnemonic, "syscall") != 0) {
- if(_numDestRegs > 0){
+ if(numDestRegs() > 0){
printReg(ss, _destRegIdx[0]);
}
- if(_numSrcRegs > 0) {
+ if(numSrcRegs() > 0) {
ss << ", ";
printReg(ss, _srcRegIdx[0]);
}
- if(_numSrcRegs > 1) {
+ if(numSrcRegs() > 1) {
ss << ", ";
printReg(ss, _srcRegIdx[1]);
}
diff --git a/src/arch/mips/isa/formats/branch.isa
b/src/arch/mips/isa/formats/branch.isa
index 7c2b27c..2d3b549 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -181,10 +181,10 @@
// either a source (the condition for conditional
// branches) or a destination (the link reg for
// unconditional branches)
- if (_numSrcRegs == 1) {
+ if (numSrcRegs() == 1) {
printReg(ss, _srcRegIdx[0]);
ss << ", ";
- } else if(_numSrcRegs == 2) {
+ } else if(numSrcRegs() == 2) {
printReg(ss, _srcRegIdx[0]);
ss << ", ";
printReg(ss, _srcRegIdx[1]);
@@ -212,15 +212,15 @@
if ( strcmp(mnemonic,"jal") == 0 ) {
Addr npc = pc + 4;
ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
- } else if (_numSrcRegs == 0) {
+ } else if (numSrcRegs() == 0) {
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(disp)) != symtab->end())
ss << it->name;
else
ccprintf(ss, "0x%x", disp);
- } else if (_numSrcRegs == 1) {
+ } else if (numSrcRegs() == 1) {
printReg(ss, _srcRegIdx[0]);
- } else if(_numSrcRegs == 2) {
+ } else if(numSrcRegs() == 2) {
printReg(ss, _srcRegIdx[0]);
ss << ", ";
printReg(ss, _srcRegIdx[1]);
diff --git a/src/arch/mips/isa/formats/dsp.isa
b/src/arch/mips/isa/formats/dsp.isa
index 12af2d6..a3fcb32 100644
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -124,7 +124,7 @@
%(op_wb)s;
//If there are 2 Destination Registers then
//concatenate the values for the traceData
- if(traceData && _numDestRegs == 2) {
+ if(traceData && numDestRegs() == 2) {
// FIXME - set the trace value correctly here
//uint64_t hilo_final_val = (uint64_t)HI_RD_SEL <<
32 | LO_RD_SEL;
//traceData->setData(hilo_final_val);
diff --git a/src/arch/mips/isa/formats/fp.isa
b/src/arch/mips/isa/formats/fp.isa
index 5d8f107..a1ed3a3 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -64,12 +64,12 @@
ccprintf(ss,"%d",CC);
- if (_numSrcRegs > 0) {
+ if (numSrcRegs() > 0) {
ss << ", ";
printReg(ss, _srcRegIdx[0]);
}
- if (_numSrcRegs > 1) {
+ if (numSrcRegs() > 1) {
ss << ", ";
printReg(ss, _srcRegIdx[1]);
}
diff --git a/src/arch/mips/isa/formats/int.isa
b/src/arch/mips/isa/formats/int.isa
index c48ad11..57abe26 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -186,7 +186,7 @@
// just print the first dest... if there's a second one,
// it's generally implicit
- if (_numDestRegs > 0) {
+ if (numDestRegs() > 0) {
printReg(ss, _destRegIdx[0]);
ss << ", ";
}
@@ -194,11 +194,11 @@
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
- if (_numSrcRegs > 0) {
+ if (numSrcRegs() > 0) {
printReg(ss, _srcRegIdx[0]);
}
- if (_numSrcRegs > 1) {
+ if (numSrcRegs() > 1) {
ss << ", ";
printReg(ss, _srcRegIdx[1]);
}
@@ -215,11 +215,11 @@
ccprintf(ss, "%-10s ", mnemonic);
// Destination Registers are implicit for HI/LO ops
- if (_numSrcRegs > 0) {
+ if (numSrcRegs() > 0) {
printReg(ss, _srcRegIdx[0]);
}
- if (_numSrcRegs > 1) {
+ if (numSrcRegs() > 1) {
ss << ", ";
printReg(ss, _srcRegIdx[1]);
}
@@ -235,9 +235,9 @@
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
+ if (numDestRegs() > 0 && _destRegIdx[0].index() < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
+ } else if (numSrcRegs() > 0 && _srcRegIdx[0].index() < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -252,9 +252,9 @@
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
+ if (numDestRegs() > 0 && _destRegIdx[0].index() < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
+ } else if (numSrcRegs() > 0 && _srcRegIdx[0].index() < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -269,9 +269,9 @@
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
+ if (numDestRegs() > 0 && _destRegIdx[0].index() < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
+ } else if (numSrcRegs() > 0 && _srcRegIdx[0].index() < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -286,13 +286,13 @@
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0) {
+ if (numDestRegs() > 0) {
printReg(ss, _destRegIdx[0]);
}
ss << ", ";
- if (_numSrcRegs > 0) {
+ if (numSrcRegs() > 0) {
printReg(ss, _srcRegIdx[0]);
ss << ", ";
}
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index aaebf35..3deef88 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -32,7 +32,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/mips/generated/max_inst_regs.hh"
#include "base/logging.hh"
#include "base/types.hh"
@@ -41,10 +40,6 @@
namespace MipsISA
{
-using MipsISAInst::MaxInstSrcRegs;
-using MipsISAInst::MaxInstDestRegs;
-using MipsISAInst::MaxMiscDestRegs;
-
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
const int NumIntSpecialRegs = 9;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index a6d28a8..8e82394 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -31,19 +31,11 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/power/generated/max_inst_regs.hh"
#include "arch/power/miscregs.hh"
#include "base/types.hh"
namespace PowerISA {
-using PowerISAInst::MaxInstSrcRegs;
-using PowerISAInst::MaxInstDestRegs;
-
-// Power writes a misc register outside of the isa parser, so it can't
-// be detected by it. Manually add it here.
-const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
-
// Not applicable to Power
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 7ce59e3..e08dfbb 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -52,15 +52,10 @@
#include "arch/generic/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/riscv/generated/max_inst_regs.hh"
#include "base/types.hh"
namespace RiscvISA {
-using RiscvISAInst::MaxInstSrcRegs;
-using RiscvISAInst::MaxInstDestRegs;
-const int MaxMiscDestRegs = 2;
-
// Not applicable to RISC-V
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
index 52517e6..ee77de5 100644
--- a/src/arch/sparc/insts/branch.cc
+++ b/src/arch/sparc/insts/branch.cc
@@ -46,8 +46,8 @@
std::stringstream response;
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
- if (_numDestRegs && _numSrcRegs)
+ printRegArray(response, _srcRegIdx);
+ if (numDestRegs() && numSrcRegs())
response << ", ";
printDestReg(response, 0);
@@ -61,11 +61,11 @@
std::stringstream response;
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
- if (_numSrcRegs > 0)
+ printRegArray(response, _srcRegIdx);
+ if (numSrcRegs() > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
- if (_numDestRegs > 0)
+ if (numDestRegs() > 0)
response << ", ";
printDestReg(response, 0);
diff --git a/src/arch/sparc/insts/integer.cc
b/src/arch/sparc/insts/integer.cc
index b92afe2..a90b550 100644
--- a/src/arch/sparc/insts/integer.cc
+++ b/src/arch/sparc/insts/integer.cc
@@ -55,7 +55,7 @@
const Loader::SymbolTable *symbab) const
{
if (!std::strcmp(mnemonic, "or")) {
- if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
+ if (numSrcRegs() > 0 && _srcRegIdx[0].index() == 0) {
if (imm == 0) {
printMnemonic(os, "clr");
} else {
@@ -83,8 +83,8 @@
if (printPseudoOps(response, pc, symtab))
return response.str();
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
- if (_numDestRegs && _numSrcRegs)
+ printRegArray(response, _srcRegIdx);
+ if (numDestRegs() && numSrcRegs())
response << ", ";
printDestReg(response, 0);
return response.str();
@@ -98,11 +98,11 @@
if (printPseudoOps(response, pc, symtab))
return response.str();
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
- if (_numSrcRegs > 0)
+ printRegArray(response, _srcRegIdx);
+ if (numSrcRegs() > 0)
response << ", ";
ccprintf(response, "%#x", imm);
- if (_numDestRegs > 0)
+ if (numDestRegs() > 0)
response << ", ";
printDestReg(response, 0);
return response.str();
diff --git a/src/arch/sparc/insts/static_inst.cc
b/src/arch/sparc/insts/static_inst.cc
index 9e7bc67..69f7255 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -59,15 +59,16 @@
}
void
-SparcStaticInst::printRegArray(std::ostream &os, const RegId indexArray[],
- int num) const
+SparcStaticInst::printRegArray(std::ostream &os,
+ const std::vector<RegId> &indexArray) const
{
- if (num <= 0)
- return;
- printReg(os, indexArray[0]);
- for (int x = 1; x < num; x++) {
- os << ", ";
- printReg(os, indexArray[x]);
+ bool first = true;
+ for (auto idx: indexArray) {
+ if (!first)
+ os << ", ";
+ else
+ first = false;
+ printReg(os, idx);
}
}
@@ -80,14 +81,14 @@
void
SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
{
- if (_numSrcRegs > reg)
+ if (numSrcRegs() > reg)
printReg(os, _srcRegIdx[reg]);
}
void
SparcStaticInst::printDestReg(std::ostream &os, int reg) const
{
- if (_numDestRegs > reg)
+ if (numDestRegs() > reg)
printReg(os, _destRegIdx[reg]);
}
@@ -256,17 +257,17 @@
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
- if (_numSrcRegs > 0)
+ if (numSrcRegs() > 0)
printReg(ss, _srcRegIdx[0]);
- if (_numSrcRegs > 1) {
+ if (numSrcRegs() > 1) {
ss << ",";
printReg(ss, _srcRegIdx[1]);
}
// just print the first dest... if there's a second one,
// it's generally implicit
- if (_numDestRegs > 0) {
- if (_numSrcRegs > 0)
+ if (numDestRegs() > 0) {
+ if (numSrcRegs() > 0)
ss << ",";
printReg(ss, _destRegIdx[0]);
}
diff --git a/src/arch/sparc/insts/static_inst.hh
b/src/arch/sparc/insts/static_inst.hh
index fcfb522..d9ad4db 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -98,8 +98,7 @@
void printSrcReg(std::ostream &os, int reg) const;
void printDestReg(std::ostream &os, int reg) const;
- void printRegArray(std::ostream &os,
- const RegId indexArray[], int num) const;
+ void printRegArray(std::ostream &os, const std::vector<RegId> &) const;
void advancePC(PCState &pcState) const override;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 6fd6577..0602176 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -31,7 +31,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/sparc/generated/max_inst_regs.hh"
#include "arch/sparc/miscregs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "base/types.hh"
@@ -39,10 +38,6 @@
namespace SparcISA
{
-using SparcISAInst::MaxInstSrcRegs;
-using SparcISAInst::MaxInstDestRegs;
-using SparcISAInst::MaxMiscDestRegs;
-
// Not applicable to SPARC
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c041a07..74cc528 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,7 +41,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/x86/generated/max_inst_regs.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/misc.hh"
@@ -49,9 +48,7 @@
namespace X86ISA
{
-using X86ISAInst::MaxInstSrcRegs;
-using X86ISAInst::MaxInstDestRegs;
-using X86ISAInst::MaxMiscDestRegs;
+
const int NumMiscRegs = NUM_MISCREGS;
const int NumIntArchRegs = NUM_INTREGS;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 194d77b..30f3815 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -92,11 +92,6 @@
// The list of instructions iterator type.
typedef typename std::list<DynInstPtr>::iterator ListIt;
- enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
- };
-
protected:
enum Status {
IqEntry, /// Instruction is in the IQ
@@ -186,7 +181,7 @@
/** Whether or not the source register is ready.
* @todo: Not sure this should be here vs the derived class.
*/
- std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
+ std::vector<bool> _readySrcRegIdx;
public:
/** The thread this instruction is from. */
@@ -251,22 +246,22 @@
/** Flattened register index of the destination registers of this
* instruction.
*/
- std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
+ std::vector<RegId> _flatDestRegIdx;
/** Physical register index of the destination registers of this
* instruction.
*/
- std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
+ std::vector<PhysRegIdPtr> _destRegIdx;
/** Physical register index of the source registers of this
* instruction.
*/
- std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
+ std::vector<PhysRegIdPtr> _srcRegIdx;
/** Physical register index of the previous producers of the
* architected destinations.
*/
- std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
+ std::vector<PhysRegIdPtr> _prevDestRegIdx;
public:
@@ -378,7 +373,7 @@
PhysRegIdPtr
renamedSrcRegIdx(int idx) const
{
- assert(TheISA::MaxInstSrcRegs > idx);
+ assert(idx < _srcRegIdx.size());
return _srcRegIdx[idx];
}
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index bfe8ff5..f75a3d2 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -64,10 +64,15 @@
: staticInst(_staticInst), cpu(cpu),
thread(nullptr),
traceData(nullptr),
+ _readySrcRegIdx(_staticInst->numSrcRegs()),
macroop(_macroop),
memData(nullptr),
savedReq(nullptr),
- reqToVerify(nullptr)
+ reqToVerify(nullptr),
+ _flatDestRegIdx(_staticInst->numDestRegs()),
+ _destRegIdx(_staticInst->numDestRegs()),
+ _srcRegIdx(_staticInst->numSrcRegs()),
+ _prevDestRegIdx(_staticInst->numDestRegs())
{
seqNum = seq_num;
@@ -80,7 +85,14 @@
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
- : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
+ : staticInst(_staticInst),
+ traceData(NULL),
+ _readySrcRegIdx(_staticInst->numSrcRegs()),
+ macroop(_macroop),
+ _flatDestRegIdx(_staticInst->numDestRegs()),
+ _destRegIdx(_staticInst->numDestRegs()),
+ _srcRegIdx(_staticInst->numSrcRegs()),
+ _prevDestRegIdx(_staticInst->numDestRegs())
{
seqNum = 0;
initVars();
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index b90e277..1e4bc5d 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -227,7 +227,7 @@
/** Flat register indices so that, when clearing the scoreboard, we
* have the same register indices as when the instruction was marked
* up */
- RegId flatDestRegIdx[TheISA::MaxInstDestRegs];
+ std::vector<RegId> flatDestRegIdx;
public:
MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) :
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index c0846c7..1aa23e3 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -114,6 +114,7 @@
StaticInstPtr staticInst = inst->staticInst;
unsigned int num_dests = staticInst->numDestRegs();
+ flatDestRegIdx.reserve(num_dests);
/** Mark each destination register */
for (unsigned int dest_index = 0; dest_index < num_dests;
dest_index++)
@@ -126,7 +127,7 @@
if (mark_unpredictable)
numUnpredictableResults[index]++;
- inst->flatDestRegIdx[dest_index] = reg;
+ inst->flatDestRegIdx.push_back(reg);
numResults[index]++;
returnCycle[index] = retire_time;
@@ -142,8 +143,8 @@
*inst, index, numResults[index], returnCycle[index]);
} else {
/* Use ZeroReg to mark invalid/untracked dests */
- inst->flatDestRegIdx[dest_index] = RegId(IntRegClass,
- TheISA::ZeroReg);
+ inst->flatDestRegIdx.push_back(
+ RegId(IntRegClass, TheISA::ZeroReg));
}
}
}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8172b9a..f8cd545 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -68,11 +68,6 @@
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;
using VecPredRegContainer = TheISA::VecPredRegContainer;
- enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
- };
-
public:
/** BaseDynInst constructor given a binary instruction. */
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
@@ -105,17 +100,13 @@
using BaseDynInst<Impl>::_destRegIdx;
/** Values to be written to the destination misc. registers. */
- std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+ std::vector<RegVal> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to
defer
* the write accesses to the misc. registers until the commit stage,
when
* the instruction is out of its speculative state.
*/
- std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
-
- /** Number of destination misc. registers. */
- uint8_t _numDestMiscRegs;
-
+ std::vector<short> _destMiscRegIdx;
public:
#if TRACING_ON
@@ -151,17 +142,15 @@
* committed instead of making a new entry. If not, make a new
* entry and record the write.
*/
- for (int idx = 0; idx < _numDestMiscRegs; idx++) {
+ for (int idx = 0; idx < _destMiscRegIdx.size(); idx++) {
if (_destMiscRegIdx[idx] == misc_reg) {
_destMiscRegVal[idx] = val;
return;
}
}
- assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
- _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
- _destMiscRegVal[_numDestMiscRegs] = val;
- _numDestMiscRegs++;
+ _destMiscRegIdx.push_back(misc_reg);
+ _destMiscRegVal.push_back(val);
}
/** Reads a misc. register, including any side-effects the read
@@ -197,7 +186,7 @@
bool no_squash_from_TC = this->thread->noSquashFromTC;
this->thread->noSquashFromTC = true;
- for (int i = 0; i < _numDestMiscRegs; i++)
+ for (int i = 0; i < _destMiscRegVal.size(); i++)
this->cpu->setMiscReg(
_destMiscRegIdx[i], _destMiscRegVal[i],
this->threadNumber);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 6c6625c..059d256 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -49,7 +49,9 @@
const StaticInstPtr ¯oop,
TheISA::PCState pc, TheISA::PCState
predPC,
InstSeqNum seq_num, O3CPU *cpu)
- : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
+ : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu),
+ _destMiscRegVal(staticInst->numMiscDestRegs()),
+ _destMiscRegIdx(staticInst->numMiscDestRegs())
{
initVars();
}
@@ -57,7 +59,9 @@
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
- : BaseDynInst<Impl>(_staticInst, _macroop)
+ : BaseDynInst<Impl>(_staticInst, _macroop),
+ _destMiscRegVal(_staticInst->numMiscDestRegs()),
+ _destMiscRegIdx(_staticInst->numMiscDestRegs())
{
initVars();
}
@@ -102,10 +106,6 @@
void
BaseO3DynInst<Impl>::initVars()
{
- this->_readySrcRegIdx.reset();
-
- _numDestMiscRegs = 0;
-
#if TRACING_ON
// Value -1 indicates that particular phase
// hasn't happened (yet).
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 6556170..af5e380 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -88,11 +88,6 @@
/// Binary extended machine instruction type.
typedef TheISA::ExtMachInst ExtMachInst;
- enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
- };
-
protected:
/// Flag values for this instruction.
@@ -101,15 +96,10 @@
/// See opClass().
OpClass _opClass;
- /// See numSrcRegs().
- int8_t _numSrcRegs;
-
- /// See numDestRegs().
- int8_t _numDestRegs;
-
/// The following are used to track physical register usage
/// for machines with separate int & FP reg files.
//@{
+ int8_t _numMiscDestRegs;
int8_t _numFPDestRegs;
int8_t _numIntDestRegs;
int8_t _numCCDestRegs;
@@ -132,9 +122,11 @@
/// machines with vector and predicate register files.
//@{
/// Number of source registers.
- int8_t numSrcRegs() const { return _numSrcRegs; }
+ int8_t numSrcRegs() const { return _srcRegIdx.size(); }
/// Number of destination registers.
- int8_t numDestRegs() const { return _numDestRegs; }
+ int8_t numDestRegs() const { return _destRegIdx.size(); }
+ /// Number of misc destination regs.
+ int8_t numMiscDestRegs() const { return _numMiscDestRegs; }
/// Number of floating-point destination regs.
int8_t numFPDestRegs() const { return _numFPDestRegs; }
/// Number of integer destination regs.
@@ -248,9 +240,9 @@
protected:
/// See destRegIdx().
- RegId _destRegIdx[MaxInstDestRegs];
+ std::vector<RegId> _destRegIdx;
/// See srcRegIdx().
- RegId _srcRegIdx[MaxInstSrcRegs];
+ std::vector<RegId> _srcRegIdx;
/**
* Base mnemonic (e.g., "add"). Used by generateDisassembly()
@@ -278,7 +270,7 @@
/// the fields that are meaningful for the particular
/// instruction.
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass
__opClass)
- : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
+ : _opClass(__opClass), _numMiscDestRegs(0),
_numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
_numVecDestRegs(0), _numVecElemDestRegs(0),
_numVecPredDestRegs(0),
machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index a978903..e013825 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -1227,7 +1227,7 @@
// Repeated field
element->clearRegDep();
- assert((pkt_msg.reg_dep()).size() <= TheISA::MaxInstSrcRegs);
+ element->regDep.reserve(pkt_msg.reg_dep().size());
for (int i = 0; i < (pkt_msg.reg_dep()).size(); i++) {
// There is a possibility that an instruction has both, a
register
// and order dependency on an instruction. In such a case, the
@@ -1237,10 +1237,10 @@
duplicate |= (pkt_msg.reg_dep(i) == element->robDep[j]);
}
if (!duplicate) {
- element->regDep[element->numRegDep] = pkt_msg.reg_dep(i);
- element->numRegDep += 1;
+ element->regDep.push_back(pkt_msg.reg_dep(i));
}
}
+ element->numRegDep = element->regDep.size();
// Optional fields
if (pkt_msg.has_p_addr())
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index ba1c5e6..93dd0c5 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -589,9 +589,6 @@
/** Typedef for the array containing the ROB dependencies */
typedef std::array<NodeSeqNum, maxRobDep> RobDepArray;
- /** Typedef for the array containing the register dependencies
*/
- typedef std::array<NodeSeqNum, TheISA::MaxInstSrcRegs>
RegDepArray;
-
/** Instruction sequence number */
NodeSeqNum seqNum;
@@ -629,7 +626,7 @@
* Array of register dependencies (incoming) if any. Maximum
number
* of source registers used to set maximum size of the array
*/
- RegDepArray regDep;
+ std::vector<NodeSeqNum> regDep;
/** Number of register dependencies */
uint8_t numRegDep;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1f9d85c4ddc6fd46084f409592fb5f5bce480ce9
Gerrit-Change-Number: 35821
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