Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35819 )
Change subject: arch: Put isa_parser operands into families.
......................................................................
arch: Put isa_parser operands into families.
When creating a new operand class, it will be associated with a family
to keep, for instance, the operands for different ISAs separate from one
another. To create a new IntReg operand for ARM for instance, you might
one day declare one like this:
arm_operands = isa_parser.operands.families['ARM']
class ArmIntReg(arm_operands.IntReg):
abstract = True
dflt_ext = 'uw'
class Rd(ArmIntReg):
reg_spec = 'RD'
Then when you define an ARM instruction, you would tell it to use
operand family "ARM". Also, that operand family will automatically end
up with classes attached to it with the names ArmIntReg and Rd which can
be further subclassed, or referred to in a different body of code.
Change-Id: Idef457a917ccaafd299e3b8621544ee104d44c35
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/isa_parser.py
M src/arch/isa_parser/operand_list.py
R src/arch/isa_parser/operands.py
M src/arch/mips/isa/operands.isa
M src/arch/power/isa/operands.isa
M src/arch/riscv/isa/operands.isa
M src/arch/sparc/isa/operands.isa
M src/arch/x86/isa/operands.isa
9 files changed, 204 insertions(+), 128 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 134c51f..961008b 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -681,7 +681,7 @@
'XURc' : intRegX64('urc'),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
+ 'Mem': ('Memory', 'uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
#PCState fields
'RawPC': pcStateReg('pc', srtPC),
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index 999d92f..80d50b7 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -44,9 +44,10 @@
# get type names
from types import *
+from . import operands
+
from m5.util.grammar import Grammar
from .operand_list import *
-from .operand_types import *
from .util import *
debug=False
@@ -466,16 +467,13 @@
# variable to hold templates
self.templateMap = {}
- # variable to hold operands
- self.operandNameMap = {}
-
- # Regular expressions for working with operands
- self._operandsRE = None
- self._operandsWithExtRE = None
-
# This dictionary maps format name strings to Format objects.
self.formatMap = {}
+ # The operand family of this ISA. This should be named after the
ISA,
+ # but for now just call it 'main'.
+ self.operandFamily = operands.Family('main')
+
# Track open files and, if applicable, how many chunks it has been
# split into so far.
self.files = {}
@@ -505,16 +503,6 @@
self.maxInstDestRegs = 0
self.maxMiscDestRegs = 0
- def operandsRE(self):
- if not self._operandsRE:
- self.buildOperandREs()
- return self._operandsRE
-
- def operandsWithExtRE(self):
- if not self._operandsWithExtRE:
- self.buildOperandREs()
- return self._operandsWithExtRE
-
def __getitem__(self, i): # Allow object (self) to be
return getattr(self, i) # passed to %-substitutions
@@ -977,11 +965,11 @@
decode_block=self.exportContext["decode_block"]).emit()
# Define the mapping from operand type extensions to C++ types and
- # bit widths (stored in operandTypeMap).
+ # bit widths (stored in operandFamily.suffixes).
def p_def_operand_types(self, t):
'def_operand_types : DEF OPERAND_TYPES CODELIT SEMI'
try:
- self.operandTypeMap = eval('{' + t[3] + '}')
+ self.operandFamily.addSuffixes(eval('{' + t[3] + '}'))
except Exception as exc:
if debug:
raise
@@ -989,10 +977,10 @@
'In def operand_types: %s' % exc)
# Define the mapping from operand names to operand classes and
- # other traits. Stored in operandNameMap.
+ # other traits. Stored in operandFamily.
def p_def_operands(self, t):
'def_operands : DEF OPERANDS CODELIT SEMI'
- if not hasattr(self, 'operandTypeMap'):
+ if not self.operandFamily.suffixes:
error(t.lineno(1),
'error: operand types must be defined before operands')
try:
@@ -1429,7 +1417,6 @@
self.formatMap[id] = Format(id, params, code)
def buildOperandNameMap(self, user_dict, lineno):
- operand_name = {}
for op_name, val in user_dict.items():
# Check if extra attributes have been specified.
@@ -1469,7 +1456,7 @@
'read_code', 'write_code',
'read_predicate', 'write_predicate']
if dflt_ext:
- dflt_ctype = self.operandTypeMap[dflt_ext]
+ dflt_ctype = self.operandFamily.suffixes[dflt_ext]
attrList.extend(['dflt_ctype', 'dflt_ext'])
# reg_spec is either just a string or a dictionary
# (for elems of vector)
@@ -1485,65 +1472,19 @@
tmp_dict[attr] = eval(attr)
tmp_dict['base_name'] = op_name
- # New class name will be e.g. "IntReg_Ra"
- cls_name = base_cls_name + '_' + op_name
- # Evaluate string arg to get class object. Note that the
- # actual base class for "IntReg" is "IntRegOperand", i.e. we
- # have to append "Operand".
- try:
- base_cls = eval(base_cls_name + 'Operand')
- except NameError:
+ if not base_cls_name in self.operandFamily.allOperands:
error(lineno,
'error: unknown operand base class "%s"' %
base_cls_name)
+ base_cls = self.operandFamily.allOperands[base_cls_name]
# The following statement creates a new class called
- # <cls_name> as a subclass of <base_cls> with the attributes
+ # <op_name> as a subclass of <base_cls> with the attributes
# in tmp_dict, just as if we evaluated a class declaration.
- operand_name[op_name] = type(cls_name, (base_cls,), tmp_dict)
-
- self.operandNameMap.update(operand_name)
-
- def buildOperandREs(self):
- # Define operand variables.
- operands = list(self.operandNameMap.keys())
- # Add the elems defined in the vector operands and
- # build a map elem -> vector (used in OperandList)
- elem_to_vec = {}
- for op_name, op in self.operandNameMap.items():
- if hasattr(op, 'elems'):
- for elem in op.elems.keys():
- operands.append(elem)
- elem_to_vec[elem] = op_name
- self.elemToVector = elem_to_vec
- extensions = self.operandTypeMap.keys()
-
- operandsREString = r'''
- (?<!\w) # neg. lookbehind assertion: prevent partial matches
- ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
- (?!\w) # neg. lookahead assertion: prevent partial matches
- ''' % ('|'.join(operands), '|'.join(extensions))
-
- self._operandsRE = re.compile(operandsREString,
- re.MULTILINE | re.VERBOSE)
-
- # Same as operandsREString, but extension is mandatory, and only
two
- # groups are returned (base and ext, not full name as above).
- # Used for subtituting '_' for '.' to make C++ identifiers.
- operandsWithExtREString = r'(?<!\w)(%s)_(%s)(?!\w)' \
- % ('|'.join(operands), '|'.join(extensions))
-
- self._operandsWithExtRE = \
- re.compile(operandsWithExtREString, re.MULTILINE)
-
- def substMungedOpNames(self, code):
- '''Munge operand names in code string to make legal C++
- variable names. This means getting rid of the type extension
- if any. Will match base_name attribute of Operand object.)'''
- return self.operandsWithExtRE().sub(r'\1', code)
+ type(base_cls)(op_name, (base_cls,), tmp_dict)
def mungeSnippet(self, s):
'''Fix up code snippets for final substitution in templates.'''
if isinstance(s, str):
- return self.substMungedOpNames(substBitOps(s))
+ return self.operandFamily.substMungedOpNames(substBitOps(s))
else:
return s
diff --git a/src/arch/isa_parser/operand_list.py
b/src/arch/isa_parser/operand_list.py
index 12a23d9..9a9ccf1 100755
--- a/src/arch/isa_parser/operand_list.py
+++ b/src/arch/isa_parser/operand_list.py
@@ -51,17 +51,16 @@
code = regEx.sub('', code)
# search for operands
- for match in parser.operandsRE().finditer(code):
- op = match.groups()
- # regexp groups are operand full name, base, and extension
- (op_full, op_base, op_ext) = op
+ for match in parser.operandFamily.operandsRE().finditer(code):
+ op_base = match.group('base')
+ op_ext = match.group('ext')
# If is a elem operand, define or update the corresponding
# vector operand
isElem = False
- if op_base in parser.elemToVector:
+ if op_base in parser.operandFamily.elemToVector:
isElem = True
elem_op = (op_base, op_ext)
- op_base = parser.elemToVector[op_base]
+ op_base = parser.operandFamily.elemToVector[op_base]
op_ext = '' # use the default one
# if the token following the operand is an assignment, this is
# a destination (LHS), else it's a source (RHS)
@@ -91,8 +90,8 @@
op_desc.active_elems.append(elem_op)
else:
# new operand: create new descriptor
- op_desc = parser.operandNameMap[op_base](parser,
- op_full, op_ext, is_src, is_dest)
+ op_desc = parser.operandFamily.operands[op_base](
+ op_ext, is_src, is_dest)
# if operand is a vector elem, add the corresponding vector
# operand if not already done
if isElem:
@@ -199,15 +198,14 @@
code = regEx.sub('', code)
# search for operands
- for match in parser.operandsRE().finditer(code):
- op = match.groups()
- # regexp groups are operand full name, base, and extension
- (op_full, op_base, op_ext) = op
+ for match in parser.operandFamily.operandsRE().finditer(code):
+ op_base = match.group('base')
+ op_ext = match.group('ext')
# If is a elem operand, define or update the corresponding
# vector operand
- if op_base in parser.elemToVector:
+ if op_base in parser.operandFamily.elemToVector:
elem_op = op_base
- op_base = parser.elemToVector[elem_op]
+ op_base = parser.operandFamily.elemToVector[elem_op]
# find this op in the requestor list
op_desc = requestor_list.find_base(op_base)
if not op_desc:
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operands.py
similarity index 79%
rename from src/arch/isa_parser/operand_types.py
rename to src/arch/isa_parser/operands.py
index cd341d0..6efb868 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operands.py
@@ -37,13 +37,21 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-class Operand(object):
+from six import add_metaclass
+
+import re
+
+from .util import error
+
+class _Operand(object):
'''Base class for operand descriptors. An instance of this class
(or actually a class derived from this one) represents a specific
operand for a code block (e.g, "Rc.sq" as a dest). Intermediate
derived classes encapsulates the traits of a particular operand
type (e.g., "32-bit integer register").'''
+ abstract = True
+
src_reg_constructor = '\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s);'
dst_reg_constructor = '\n\t_destRegIdx[_numDestRegs++] =
RegId(%s, %s);'
@@ -73,8 +81,7 @@
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_ctype, self.base_name, code)
- def __init__(self, parser, full_name, ext, is_src, is_dest):
- self.full_name = full_name
+ def __init__(self, ext, is_src, is_dest):
self.ext = ext
self.is_src = is_src
self.is_dest = is_dest
@@ -86,7 +93,7 @@
self.eff_ext = self.dflt_ext
if hasattr(self, 'eff_ext'):
- self.ctype = parser.operandTypeMap[self.eff_ext]
+ self.ctype = self.family().suffixes[self.eff_ext]
# Finalize additional fields (primarily code fields). This step
# is done separately since some of these fields may depend on the
@@ -168,7 +175,8 @@
return self.ctype + ' ' + self.base_name + ' = 0;\n';
-class IntRegOperand(Operand):
+class _IntReg(_Operand):
+ abstract = True
reg_class = 'IntRegClass'
def isReg(self):
@@ -240,7 +248,8 @@
return wb
-class FloatRegOperand(Operand):
+class _FloatReg(_Operand):
+ abstract = True
reg_class = 'FloatRegClass'
def isReg(self):
@@ -303,13 +312,13 @@
}''' % (self.ctype, self.base_name, wp)
return wb
-class VecRegOperand(Operand):
+class _VecReg(_Operand):
+ abstract = True
reg_class = 'VecRegClass'
- def __init__(self, parser, full_name, ext, is_src, is_dest):
- Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
+ def __init__(self, ext, is_src, is_dest):
+ Operand.__init__(self, ext, is_src, is_dest)
self.elemExt = None
- self.parser = parser
def isReg(self):
return 1
@@ -324,7 +333,7 @@
ext = elem_ext
else:
ext = dflt_elem_ext
- ctype = self.parser.operandTypeMap[ext]
+ ctype = self.family().suffixes[ext]
return '\n\t%s %s = 0;' % (ctype, elem_name)
def makeDecl(self):
@@ -361,7 +370,7 @@
ext = elem_ext
else:
ext = dflt_elem_ext
- ctype = self.parser.operandTypeMap[ext]
+ ctype = self.family().suffixes[ext]
c_read = '\t\t%s& %s = %s[%s];\n' % \
(ctype, elem_name, self.base_name, elem_spec)
return c_read
@@ -380,10 +389,10 @@
% ('TheISA::VecRegContainer', rindex, func, rindex)
if self.elemExt:
c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' %
(self.base_name,
- rindex, self.parser.operandTypeMap[self.elemExt])
+ rindex, self.family().suffixes[self.elemExt])
if self.ext:
c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' %
(self.base_name,
- rindex, self.parser.operandTypeMap[self.ext])
+ rindex, self.family().suffixes[self.ext])
if hasattr(self, 'active_elems'):
if self.active_elems:
for elem in self.active_elems:
@@ -399,7 +408,7 @@
ext = elem_ext
else:
ext = dflt_elem_ext
- ctype = self.parser.operandTypeMap[ext]
+ ctype = self.family().suffixes[ext]
c_read = '\t\t%s = %s[%s];\n' % \
(elem_name, name, elem_spec)
return c_read
@@ -424,10 +433,10 @@
# the appropriate view
if self.elemExt:
c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % \
- (name, rindex, self.parser.operandTypeMap[self.elemExt])
+ (name, rindex, self.family().suffixes[self.elemExt])
if self.ext:
c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % \
- (name, rindex, self.parser.operandTypeMap[self.ext])
+ (name, rindex, self.family().suffixes[self.ext])
if hasattr(self, 'active_elems'):
if self.active_elems:
for elem in self.active_elems:
@@ -447,11 +456,12 @@
return wb
def finalize(self, predRead, predWrite):
- super(VecRegOperand, self).finalize(predRead, predWrite)
+ super(_VecReg, self).finalize(predRead, predWrite)
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class VecElemOperand(Operand):
+class _VecElem(_Operand):
+ abstract = True
reg_class = 'VecElemClass'
def isReg(self):
@@ -505,13 +515,10 @@
return c_write
-class VecPredRegOperand(Operand):
+class _VecPredReg(_Operand):
+ abstract = True
reg_class = 'VecPredRegClass'
- def __init__(self, parser, full_name, ext, is_src, is_dest):
- Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
- self.parser = parser
-
def isReg(self):
return 1
@@ -549,7 +556,7 @@
if self.ext:
c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % (
self.base_name, rindex,
- self.parser.operandTypeMap[self.ext])
+ self.family().suffixes[self.ext])
return c_read
def makeReadW(self, predWrite):
@@ -567,7 +574,7 @@
if self.ext:
c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' % (
self.base_name, rindex,
- self.parser.operandTypeMap[self.ext])
+ self.family().suffixes[self.ext])
return c_readw
def makeWrite(self, predWrite):
@@ -583,11 +590,12 @@
return wb
def finalize(self, predRead, predWrite):
- super(VecPredRegOperand, self).finalize(predRead, predWrite)
+ super(_VecPredReg, self).finalize(predRead, predWrite)
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class CCRegOperand(Operand):
+class _CCReg(_Operand):
+ abstract = True
reg_class = 'CCRegClass'
def isReg(self):
@@ -659,7 +667,8 @@
return wb
-class ControlRegOperand(Operand):
+class _ControlReg(_Operand):
+ abstract = True
reg_class = 'MiscRegClass'
def isReg(self):
@@ -713,7 +722,9 @@
return wb
-class MemOperand(Operand):
+class _Memory(_Operand):
+ abstract = True
+
def isMem(self):
return 1
@@ -734,7 +745,9 @@
return self.buildWriteCode()
return ''
-class PCStateOperand(Operand):
+class _PCState(_Operand):
+ abstract = True
+
def makeConstructor(self, predRead, predWrite):
return ''
@@ -766,3 +779,122 @@
def isPCState(self):
return 1
+
+families = {}
+class Family(object):
+ def buildOperandREs(self):
+ # Define operand variables.
+ operands = list(self.operands.keys())
+ # Add the elems defined in the vector operands and
+ # build a map elem -> vector (used in OperandList)
+ elem_to_vec = {}
+ for op_name, op in self.operands.items():
+ if hasattr(op, 'elems'):
+ for elem in op.elems.keys():
+ operands.append(elem)
+ elem_to_vec[elem] = op_name
+ self.elemToVector = elem_to_vec
+ extensions = self.suffixes.keys()
+
+ operandsREString = r'''
+ # neg. lookbehind assertion: prevent partial matches
+ (?<!\w)
+ # match: operand with optional '_' then suffix
+ (?:(?P<base>%s)(?:_(?P<ext>%s))?)
+ # neg. lookahead assertion: prevent partial matches
+ (?!\w)
+ ''' % ('|'.join(operands), '|'.join(extensions))
+
+ self._operandsRE = re.compile(operandsREString,
+ re.MULTILINE | re.VERBOSE)
+
+ # Same as operandsREString, but extension is mandatory, and only
two
+ # groups are returned (base and ext, not full name as above).
+ # Used for subtituting '_' for '.' to make C++ identifiers.
+ operandsWithExtREString = r'(?<!\w)(?P<base>%s)_(?P<ext>%s)(?!\w)'
\
+ % ('|'.join(operands), '|'.join(extensions))
+
+ self._operandsWithExtRE = \
+ re.compile(operandsWithExtREString, re.MULTILINE)
+
+ def operandsRE(self):
+ if not self._operandsRE:
+ self.buildOperandREs()
+ return self._operandsRE
+
+ def operandsWithExtRE(self):
+ if not self._operandsWithExtRE:
+ self.buildOperandREs()
+ return self._operandsWithExtRE
+
+ def substMungedOpNames(self, code):
+ '''Munge operand names in code string to make legal C++
+ variable names. This means getting rid of the type extension
+ if any. Will match base_name attribute of Operand object.)'''
+ return self.operandsWithExtRE().sub(r'\g<base>', code)
+
+ def addSuffixes(self, *pos_suffixes, **kw_suffixes):
+ for suffix in pos_suffixes:
+ self.suffixes.update(suffix)
+ self.suffixes.update(kw_suffixes)
+
+ def _importAbstractType(self, new_name, base):
+ tmp_dict = {
+ 'abstract': True,
+ 'family': lambda x: self,
+ }
+ self.OperandMeta(new_name, (base,), tmp_dict)
+
+ def __init__(self, name):
+ # Regular expressions for working with operands
+ self._operandsRE = None
+ self._operandsWithExtRE = None
+
+ # Make it possible to look up this family of operands by name
later.
+ assert name not in families, \
+ 'Operand family %s already exists' % name
+ families[name] = self
+ self.name = name
+
+ # All operands, even abstract ones.
+ self.allOperands = {}
+ # Only concrete operands.
+ self.operands = {}
+
+ # Operand suffixes
+ self.suffixes = {}
+
+ class OperandMeta(type):
+ def __init__(cls, name, bases, dict):
+ super(OperandMeta, cls).__init__(name, bases, dict)
+
+ # Default the name of the operand to the given name of the
+ # class.
+ op_name = self.allOperands.get('name', name)
+ assert op_name not in self.allOperands, \
+ 'Operand family %s already has an operand %s' % (
+ self.name, op_name)
+ abstract = dict.get('abstract', False)
+
+ # Make this Operand subclass available so it can then be
+ # subclassed to expand the family.
+ self.allOperands[op_name] = cls
+ if not abstract:
+ self.operands[op_name] = cls
+
+ setattr(self, op_name, cls)
+
+ self.OperandMeta = OperandMeta
+
+ # Make local versions of these operand types which are associated
with
+ # this family.
+ self._importAbstractType("Operand", _Operand)
+ self._importAbstractType("IntReg", _IntReg)
+ self._importAbstractType("FloatReg", _FloatReg)
+ self._importAbstractType("VecReg", _VecReg)
+ self._importAbstractType("VecElem", _VecElem)
+ self._importAbstractType("VecPredReg", _VecPredReg)
+ self._importAbstractType("CCReg", _CCReg)
+ self._importAbstractType("ControlReg", _ControlReg)
+ self._importAbstractType("Memory", _Memory)
+ self._importAbstractType("PCState", _PCState)
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 3cb2d43..e867917 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -144,7 +144,7 @@
'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 4),
+ 'Mem': ('Memory', 'uw', None, (None, 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index e77fde2..f571c25 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -54,7 +54,7 @@
'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
# Memory Operand
- 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
+ 'Mem': ('Memory', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
# Program counter and next
'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 78cd5f9..b99d398 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -72,7 +72,7 @@
'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
#Memory Operand
- 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),
+ 'Mem': ('Memory', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),
#Program Counter Operands
'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
diff --git a/src/arch/sparc/isa/operands.isa
b/src/arch/sparc/isa/operands.isa
index 7a2da13..2a59b4c 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -183,10 +183,15 @@
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None,
73),
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
- 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG',
None, 75),
+ 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG',
+ None, 75),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR',
+ (None, None, ['IsSerializeAfter',
+ 'IsSerializing',
+ 'IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
- 'Mem': ('Mem', 'udw', None, (None, 'IsLoad', 'IsStore'),
100)
+ 'Mem': ('Memory', 'udw', None,
+ (None, 'IsLoad', 'IsStore'), 100)
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 504deb7..173a3ce 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -206,6 +206,6 @@
'MiscRegSrc1': controlReg('src1', 211),
'TscOp': controlReg('MISCREG_TSC', 212),
'M5Reg': squashCReg('MISCREG_M5_REG', 213),
- 'Mem': ('Mem', 'uqw', None, \
+ 'Mem': ('Memory', 'uqw', None, \
(None, 'IsLoad', 'IsStore'), 300)
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idef457a917ccaafd299e3b8621544ee104d44c35
Gerrit-Change-Number: 35819
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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