Attention is currently required from: Ciro Santilli, Nikos Nikoleris.
Hello Ciro Santilli, Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/37615
to review the following change.
Change subject: arch-arm: Add SECURE_RD/WR flags to miscRegInfo
......................................................................
arch-arm: Add SECURE_RD/WR flags to miscRegInfo
The introduction of Secure EL2 in gem5 requires the introduction
of new miscReg flags as there are some EL2 registers which are
accessible from secure mode only
Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Ciro Santilli <ciro.santi...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
3 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6b9dd3c..dce5e37 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -252,12 +252,30 @@
privNonSecureRead(v);
return *this;
}
+ chain hypE2HSecureRead(bool v = true) const {
+ info[MISCREG_HYP_E2H_S_RD] = v;
+ return *this;
+ }
+ chain hypE2HNonSecureRead(bool v = true) const {
+ info[MISCREG_HYP_E2H_NS_RD] = v;
+ return *this;
+ }
chain hypE2HRead(bool v = true) const {
- info[MISCREG_HYP_E2H_RD] = v;
+ hypE2HSecureRead(v);
+ hypE2HNonSecureRead(v);
+ return *this;
+ }
+ chain hypE2HSecureWrite(bool v = true) const {
+ info[MISCREG_HYP_E2H_S_WR] = v;
+ return *this;
+ }
+ chain hypE2HNonSecureWrite(bool v = true) const {
+ info[MISCREG_HYP_E2H_NS_WR] = v;
return *this;
}
chain hypE2HWrite(bool v = true) const {
- info[MISCREG_HYP_E2H_WR] = v;
+ hypE2HSecureWrite(v);
+ hypE2HNonSecureWrite(v);
return *this;
}
chain hypE2H(bool v = true) const {
@@ -265,14 +283,39 @@
hypE2HWrite(v);
return *this;
}
+ chain hypSecureRead(bool v = true) const {
+ info[MISCREG_HYP_S_RD] = v;
+ return *this;
+ }
+ chain hypNonSecureRead(bool v = true) const {
+ info[MISCREG_HYP_NS_RD] = v;
+ return *this;
+ }
chain hypRead(bool v = true) const {
hypE2HRead(v);
- info[MISCREG_HYP_RD] = v;
+ hypSecureRead(v);
+ hypNonSecureRead(v);
+ return *this;
+ }
+ chain hypSecureWrite(bool v = true) const {
+ info[MISCREG_HYP_S_WR] = v;
+ return *this;
+ }
+ chain hypNonSecureWrite(bool v = true) const {
+ info[MISCREG_HYP_NS_WR] = v;
return *this;
}
chain hypWrite(bool v = true) const {
hypE2HWrite(v);
- info[MISCREG_HYP_WR] = v;
+ hypSecureWrite(v);
+ hypNonSecureWrite(v);
+ return *this;
+ }
+ chain hypSecure(bool v = true) const {
+ hypE2HSecureRead(v);
+ hypE2HSecureWrite(v);
+ hypSecureRead(v);
+ hypSecureWrite(v);
return *this;
}
chain hyp(bool v = true) const {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 932abc3..5b97b07 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1229,7 +1229,7 @@
miscRegInfo[reg][MISCREG_MON_NS1_RD];
break;
case MODE_HYP:
- canRead = miscRegInfo[reg][MISCREG_HYP_RD];
+ canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
break;
default:
undefined = true;
@@ -1275,7 +1275,7 @@
miscRegInfo[reg][MISCREG_MON_NS1_WR];
break;
case MODE_HYP:
- canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
+ canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
break;
default:
undefined = true;
@@ -1396,8 +1396,13 @@
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
case EL2:
- return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
- miscRegInfo[reg][MISCREG_HYP_RD];
+ if (el2_host) {
+ return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
+ miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
+ } else {
+ return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
+ miscRegInfo[reg][MISCREG_HYP_NS_RD];
+ }
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
@@ -1427,8 +1432,13 @@
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
case EL2:
- return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
- miscRegInfo[reg][MISCREG_HYP_WR];
+ if (el2_host) {
+ return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
+ miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
+ } else {
+ return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
+ miscRegInfo[reg][MISCREG_HYP_NS_WR];
+ }
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f683297..f6188a0 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1119,11 +1119,15 @@
MISCREG_PRI_S_RD,
MISCREG_PRI_S_WR,
// Hypervisor mode
- MISCREG_HYP_RD,
- MISCREG_HYP_WR,
+ MISCREG_HYP_NS_RD,
+ MISCREG_HYP_NS_WR,
+ MISCREG_HYP_S_RD,
+ MISCREG_HYP_S_WR,
// Hypervisor mode, HCR_EL2.E2H == 1
- MISCREG_HYP_E2H_RD,
- MISCREG_HYP_E2H_WR,
+ MISCREG_HYP_E2H_NS_RD,
+ MISCREG_HYP_E2H_NS_WR,
+ MISCREG_HYP_E2H_S_RD,
+ MISCREG_HYP_E2H_S_WR,
// Monitor mode, SCR.NS == 0
MISCREG_MON_NS0_RD,
MISCREG_MON_NS0_WR,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37615
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Gerrit-Change-Number: 37615
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Attention: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-Attention: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-MessageType: newchange
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