Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37815 )
Change subject: mem-ruby: Move CacheMemory stats used in SLICC to a Stats
group
......................................................................
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
This change moves some stats that are used in SLICC to a
separate Stats::Group.
In order to use stats in SLICC, new functions are added in
CacheMemory:
- profileDemandHit()
- profileDemandMiss()
The functions increase the corresponding stat by 1.
Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Tiago Mück <tiago.m...@arm.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
M src/mem/ruby/protocol/MI_example-cache.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
M src/mem/ruby/protocol/MOESI_hammer-cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
19 files changed, 132 insertions(+), 116 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Tiago Mück: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index c4c4c3e..5edd7db 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -439,11 +439,11 @@
}
action(p_profileMiss, "pm", desc="Profile cache miss") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(p_profileHit, "ph", desc="Profile cache hit") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(t_allocateTBE, "t", desc="allocate TBE Entry") {
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index aafe5a4..5e987c8 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -529,11 +529,11 @@
// added for profiling
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss"){
- ++L1cache.demand_misses;
+ L1cache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit"){
- ++L1cache.demand_hits;
+ L1cache.profileDemandHit();
}
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 4de4a29..46c1664 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -771,19 +771,19 @@
}
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
- ++Icache.demand_misses;
+ Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++Icache.demand_hits;
+ Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
- ++Dcache.demand_misses;
+ Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++Dcache.demand_hits;
+ Dcache.profileDemandHit();
}
// store conditionals
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index 7344ca1..bcf99ff 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -774,11 +774,11 @@
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
- ++cache.demand_misses;
+ cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
- ++cache.demand_hits;
+ cache.profileDemandHit();
}
diff --git a/src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
index a6e4faf..4d5935d 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
@@ -915,19 +915,19 @@
}
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
- ++Icache.demand_misses;
+ Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++Icache.demand_hits;
+ Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
- ++Dcache.demand_misses;
+ Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++Dcache.demand_hits;
+ Dcache.profileDemandHit();
}
// store conditionals
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 3e07e03..1a5d0e5 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -956,19 +956,19 @@
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++L1Icache.demand_hits;
+ L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
- ++L1Dcache.demand_misses;
+ L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++L1Dcache.demand_hits;
+ L1Dcache.profileDemandHit();
}
action(po_observeHit, "\ph", desc="Inform the prefetcher about the hit")
{
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
index 91f58ff..b189f71 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
@@ -732,11 +732,11 @@
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
diff --git a/src/mem/ruby/protocol/MI_example-cache.sm
b/src/mem/ruby/protocol/MI_example-cache.sm
index 2c9bdb7..e662a76 100644
--- a/src/mem/ruby/protocol/MI_example-cache.sm
+++ b/src/mem/ruby/protocol/MI_example-cache.sm
@@ -350,11 +350,11 @@
}
action(p_profileMiss, "pi", desc="Profile cache miss") {
- ++cacheMemory.demand_misses;
+ cacheMemory.profileDemandMiss();
}
action(p_profileHit, "ph", desc="Profile cache hit") {
- ++cacheMemory.demand_hits;
+ cacheMemory.profileDemandHit();
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
index fb957f0..11b53bc 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
@@ -1267,35 +1267,35 @@
}
action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
- ++L1D0cache.demand_misses;
+ L1D0cache.profileDemandMiss();
}
action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
- ++L1D1cache.demand_misses;
+ L1D1cache.profileDemandMiss();
}
action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(l10h_profileHit, "l10h", desc="l10h hit profile") {
- ++L1D0cache.demand_hits;
+ L1D0cache.profileDemandHit();
}
action(l11h_profileHit, "l11h", desc="l11h hit profile") {
- ++L1D1cache.demand_hits;
+ L1D1cache.profileDemandHit();
}
action(l1ih_profileHit, "l1lh", desc="l1ih hit profile") {
- ++L1Icache.demand_hits;
+ L1Icache.profileDemandHit();
}
action(l2h_profileHit, "l2h", desc="l2h hit profile") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
index 3f24d5a..d4c6bbc 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -1421,19 +1421,19 @@
}
action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
- ++L1D0cache.demand_misses;
+ L1D0cache.profileDemandMiss();
}
action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
- ++L1D1cache.demand_misses;
+ L1D1cache.profileDemandMiss();
}
action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 389d123..684d03e 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -639,9 +639,9 @@
//deallocated in dt_deallocateTBE (only for WB) as it checks the L3Hit
flag of the TBE entry.
action(pr_profileL3HitMiss, "pr_l3hm", desc="L3 Hit or Miss Profile") {
if (tbe.L3Hit) {
- ++L3CacheMemory.demand_hits;
+ L3CacheMemory.profileDemandHit();
} else {
- ++L3CacheMemory.demand_misses;
+ L3CacheMemory.profileDemandMiss();
}
}
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index 15bbdd3..edd1435 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -905,19 +905,19 @@
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++L1Icache.demand_hits;
+ L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
- ++L1Dcache.demand_misses;
+ L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++L1Dcache.demand_hits;
+ L1Dcache.profileDemandHit();
}
action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory
queue to the back of the queue.") {
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 9894107..b111879 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -1560,11 +1560,11 @@
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(y_copyCacheStateToDir, "y", desc="Copy cache state to directory
state") {
diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
index 17c518a..5c3d5f7 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -1549,19 +1549,19 @@
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++L1Icache.demand_hits;
+ L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
- ++L1Dcache.demand_misses;
+ L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++L1Dcache.demand_hits;
+ L1Dcache.profileDemandHit();
}
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the
incoming data and the data in the cache match") {
diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
index 119508a..2f8623a 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
@@ -981,11 +981,11 @@
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the
incoming data and the data in the cache match") {
diff --git a/src/mem/ruby/protocol/MOESI_hammer-cache.sm
b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
index 5440eb8..aba28ff 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
@@ -1266,27 +1266,27 @@
}
action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") {
- ++L1Dcache.demand_misses;
+ L1Dcache.profileDemandMiss();
}
action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") {
- ++L1Dcache.demand_hits;
+ L1Dcache.profileDemandHit();
}
action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") {
- ++L1Icache.demand_misses;
+ L1Icache.profileDemandMiss();
}
action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") {
- ++L1Icache.demand_hits;
+ L1Icache.profileDemandHit();
}
action(uu_profileL2Miss, "\um", desc="Profile the demand miss") {
- ++L2cache.demand_misses;
+ L2cache.profileDemandMiss();
}
action(uu_profileL2Hit, "\uh", desc="Profile the demand hits") {
- ++L2cache.demand_hits;
+ L2cache.profileDemandHit();
}
action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the
mandatory queue to the back of the queue.") {
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index af7c017..d085fde 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -211,8 +211,8 @@
int getNumBlocks();
Addr getAddressAtIdx(int);
- Scalar demand_misses;
- Scalar demand_hits;
+ void profileDemandHit();
+ void profileDemandMiss();
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
diff --git a/src/mem/ruby/structures/CacheMemory.cc
b/src/mem/ruby/structures/CacheMemory.cc
index 3a27f8e..4c04fd7 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -68,16 +68,7 @@
p.start_index_bit, p.ruby_system),
tagArray(p.tagArrayBanks, p.tagAccessLatency,
p.start_index_bit, p.ruby_system),
- cacheMemoryStats(this),
- ADD_STAT(m_demand_hits, "Number of cache demand hits"),
- ADD_STAT(m_demand_misses, "Number of cache demand misses"),
- ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
- m_demand_hits + m_demand_misses),
- ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
- ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
- ADD_STAT(m_prefetches, "Number of prefetches",
- m_sw_prefetches + m_hw_prefetches),
- ADD_STAT(m_accessModeType, "")
+ cacheMemoryStats(this)
{
m_cache_size = p.size;
m_cache_assoc = p.assoc;
@@ -88,26 +79,6 @@
m_block_size = p.block_size; // may be 0 at this point. Updated in
init()
m_use_occupancy = dynamic_cast<ReplacementPolicy::WeightedLRU*>(
m_replacementPolicy_ptr) ? true :
false;
-
- m_sw_prefetches
- .flags(Stats::nozero);
-
- m_hw_prefetches
- .flags(Stats::nozero);
-
- m_prefetches
- .flags(Stats::nozero);
-
- m_accessModeType
- .init(RubyRequestType_NUM)
- .flags(Stats::pdf | Stats::total);
-
- for (int i = 0; i < RubyAccessMode_NUM; i++) {
- m_accessModeType
- .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
- .flags(Stats::nozero)
- ;
- }
}
void
@@ -559,7 +530,16 @@
"transaction"),
ADD_STAT(htmTransAbortReadSet, "Read set size of a aborted
transaction"),
ADD_STAT(htmTransAbortWriteSet, "Write set size of a aborted "
- "transaction")
+ "transaction"),
+ ADD_STAT(m_demand_hits, "Number of cache demand hits"),
+ ADD_STAT(m_demand_misses, "Number of cache demand misses"),
+ ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
+ m_demand_hits + m_demand_misses),
+ ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
+ ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
+ ADD_STAT(m_prefetches, "Number of prefetches",
+ m_sw_prefetches + m_hw_prefetches),
+ ADD_STAT(m_accessModeType, "")
{
numDataArrayReads
.flags(Stats::nozero);
@@ -595,6 +575,25 @@
.init(8)
.flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
+ m_sw_prefetches
+ .flags(Stats::nozero);
+
+ m_hw_prefetches
+ .flags(Stats::nozero);
+
+ m_prefetches
+ .flags(Stats::nozero);
+
+ m_accessModeType
+ .init(RubyRequestType_NUM)
+ .flags(Stats::pdf | Stats::total);
+
+ for (int i = 0; i < RubyAccessMode_NUM; i++) {
+ m_accessModeType
+ .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
+ .flags(Stats::nozero)
+ ;
+ }
}
// assumption: SLICC generated files will only call this function
@@ -738,3 +737,15 @@
DPRINTF(HtmMem, "htmCommitTransaction: read set=%u write set=%u\n",
htmReadSetSize, htmWriteSetSize);
}
+
+void
+CacheMemory::profileDemandHit()
+{
+ cacheMemoryStats.m_demand_hits++;
+}
+
+void
+CacheMemory::profileDemandMiss()
+{
+ cacheMemoryStats.m_demand_misses++;
+}
\ No newline at end of file
diff --git a/src/mem/ruby/structures/CacheMemory.hh
b/src/mem/ruby/structures/CacheMemory.hh
index c126a53..84b9d87 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -148,25 +148,6 @@
void htmCommitTransaction();
public:
- struct CacheMemoryStats : public Stats::Group
- {
- CacheMemoryStats(Stats::Group *parent);
-
- Stats::Scalar numDataArrayReads;
- Stats::Scalar numDataArrayWrites;
- Stats::Scalar numTagArrayReads;
- Stats::Scalar numTagArrayWrites;
-
- Stats::Scalar numTagArrayStalls;
- Stats::Scalar numDataArrayStalls;
-
- // hardware transactional memory
- Stats::Histogram htmTransCommitReadSet;
- Stats::Histogram htmTransCommitWriteSet;
- Stats::Histogram htmTransAbortReadSet;
- Stats::Histogram htmTransAbortWriteSet;
- };
-
int getCacheSize() const { return m_cache_size; }
int getCacheAssoc() const { return m_cache_assoc; }
int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
@@ -224,17 +205,41 @@
*/
bool m_use_occupancy;
+ private:
+ struct CacheMemoryStats : public Stats::Group
+ {
+ CacheMemoryStats(Stats::Group *parent);
+
+ Stats::Scalar numDataArrayReads;
+ Stats::Scalar numDataArrayWrites;
+ Stats::Scalar numTagArrayReads;
+ Stats::Scalar numTagArrayWrites;
+
+ Stats::Scalar numTagArrayStalls;
+ Stats::Scalar numDataArrayStalls;
+
+ // hardware transactional memory
+ Stats::Histogram htmTransCommitReadSet;
+ Stats::Histogram htmTransCommitWriteSet;
+ Stats::Histogram htmTransAbortReadSet;
+ Stats::Histogram htmTransAbortWriteSet;
+
+ Stats::Scalar m_demand_hits;
+ Stats::Scalar m_demand_misses;
+ Stats::Formula m_demand_accesses;
+
+ Stats::Scalar m_sw_prefetches;
+ Stats::Scalar m_hw_prefetches;
+ Stats::Formula m_prefetches;
+
+ Stats::Vector m_accessModeType;
+ } cacheMemoryStats;
+
public:
- CacheMemoryStats cacheMemoryStats;
- Stats::Scalar m_demand_hits;
- Stats::Scalar m_demand_misses;
- Stats::Formula m_demand_accesses;
-
- Stats::Scalar m_sw_prefetches;
- Stats::Scalar m_hw_prefetches;
- Stats::Formula m_prefetches;
-
- Stats::Vector m_accessModeType;
+ // These function increment the number of demand hits/misses by one
+ // each time they are called
+ void profileDemandHit();
+ void profileDemandMiss();
};
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Gerrit-Change-Number: 37815
Gerrit-PatchSet: 12
Gerrit-Owner: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Daniel Gerzhoy <daniel.gerz...@gmail.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
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