Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40917 )
Change subject: arch-power: Fix logical instructions
......................................................................
arch-power: Fix logical instructions
Now that 64-bit registers are being used, the instructions
performing comparisons must use the entire 64 bits of the
register operands. Also, most of these instructions need
to determine the nature of the result if the Rc bit is set.
This fixes the following instructions.
* AND (and[.])
* OR (or[.])
* XOR (xor[.])
* NAND (nand[.])
* NOR (nor[.])
* Equivalent (eqv[.])
* AND with Complement (andc[.])
* OR with Complement (orc[.])
* Extend Sign Byte (extsb[.])
* Extend Sign Halfword (extsh[.])
* Count Leading Zeros Word (cntlzw[.])
* Compare Bytes (cmpb)
Change-Id: Ifecb0779fa6e2062d382f9abf8b2cfaf7cea3c96
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/isa/decoder.isa
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d5b2a34..0932ce4 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -487,25 +487,28 @@
// Integer logic instructions use source registers Rs and Rb,
// with destination register Ra.
format IntLogicOp {
- 28: and({{ Ra = Rs & Rb; }});
- 316: xor({{ Ra = Rs ^ Rb; }});
- 476: nand({{ Ra = ~(Rs & Rb); }});
- 444: or({{ Ra = Rs | Rb; }});
- 124: nor({{ Ra = ~(Rs | Rb); }});
- 60: andc({{ Ra = Rs & ~Rb; }});
- 954: extsb({{ Ra = sext<8>(Rs); }});
- 284: eqv({{ Ra = ~(Rs ^ Rb); }});
- 412: orc({{ Ra = Rs | ~Rb; }});
- 922: extsh({{ Ra = sext<16>(Rs); }});
- 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
+ 28: and({{ Ra = Rs & Rb; }}, true);
+ 316: xor({{ Ra = Rs ^ Rb; }}, true);
+ 476: nand({{ Ra = ~(Rs & Rb); }}, true);
+ 444: or({{ Ra = Rs | Rb; }}, true);
+ 124: nor({{ Ra = ~(Rs | Rb); }}, true);
+ 60: andc({{ Ra = Rs & ~Rb; }}, true);
+ 284: eqv({{ Ra = ~(Rs ^ Rb); }}, true);
+ 412: orc({{ Ra = Rs | ~Rb; }}, true);
+ 954: extsb({{ Ra = Rs_sb; }}, true);
+ 922: extsh({{ Ra = Rs_sh; }}, true);
+ 26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
+
508: cmpb({{
- uint32_t val = 0;
- for (int n = 0; n < 32; n += 8) {
- if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
- val = insertBits(val, n+7, n, 0xff);
+ uint64_t mask = 0xff;
+ uint64_t res = 0;
+ for (int i = 0; i < 8; ++i) {
+ if ((Rs & mask) == (Rb & mask)) {
+ res |= mask;
}
+ mask <<= 8;
}
- Ra = val;
+ Ra = res;
}});
24: slw({{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifecb0779fa6e2062d382f9abf8b2cfaf7cea3c96
Gerrit-Change-Number: 40917
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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