Matthew Poremba has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/47102 )

Change subject: arch-vega,gpu-compute: Fix GPUStaticInst flags
......................................................................

arch-vega,gpu-compute: Fix GPUStaticInst flags

There are many missing, wrong cased, or incorrect flags in the
instructions. Added new ones to GPUStaticInstFlags.py to fix this.

Change-Id: I976cbd407a466e8ad77c84dbdc29082f49e28f3b
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/gpu-compute/GPUStaticInstFlags.py
M src/gpu-compute/gpu_static_inst.hh
3 files changed, 18 insertions(+), 7 deletions(-)



diff --git a/src/arch/amdgpu/vega/insts/instructions.cc b/src/arch/amdgpu/vega/insts/instructions.cc
index 5db3e54..cdf3c68 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -4489,7 +4489,7 @@
     Inst_SOPP__S_BARRIER::Inst_SOPP__S_BARRIER(InFmt_SOPP *iFmt)
         : Inst_SOPP(iFmt, "s_barrier")
     {
-        setFlag(Barrier);
+        setFlag(MemBarrier);
     } // Inst_SOPP__S_BARRIER

     Inst_SOPP__S_BARRIER::~Inst_SOPP__S_BARRIER()
diff --git a/src/gpu-compute/GPUStaticInstFlags.py b/src/gpu-compute/GPUStaticInstFlags.py
index 1dc143c..bb3d7b9 100644
--- a/src/gpu-compute/GPUStaticInstFlags.py
+++ b/src/gpu-compute/GPUStaticInstFlags.py
@@ -38,7 +38,6 @@

     vals = [
         # Op types
-        'ALU',               # ALU op
         'Branch',            # Branch instruction
         'CondBranch',        # Conditinal Branch instruction
         'Nop',               # No-op (no effect at all)
@@ -49,6 +48,10 @@
         'SpecialOp',         # Special op
         'Waitcnt',           # Is a waitcnt instruction
         'Sleep',             # Is a sleep instruction
+        'LDS',               # Local data share
+        'TextureMem',        # Vector memory (MUBUF, MTBUF)
+        'SMEM',              # Scalar memory
+        'ALU',               # ALU op

         # Memory ops
         'MemBarrier',        # Barrier instruction
@@ -63,13 +66,15 @@
         'AtomicNoReturn',    # Atomic instruction that doesn't return data

         # Instruction attributes
+ 'ReturnToLDS', # Buffer memory load that returns to LDS not VGPRs
         'Scalar',            # A scalar (not vector) operation
+        'Internal',          # Internally executed operation
         'ReadsSCC',          # The instruction reads SCC
         'WritesSCC',         # The instruction writes SCC
         'ReadsVCC',          # The instruction reads VCC
         'WritesVCC',         # The instruction writes VCC
-        'ReadsEXEC',         # The instruction reads Exec Mask
-        'WritesEXEC',        # The instruction writes Exec Mask
+        'ReadsExec',         # The instruction reads Exec Mask
+        'WritesExec',        # The instruction writes Exec Mask
         'ReadsMode',         # The instruction reads Mode register
         'WritesMode',        # The instruction writes Mode register
         'IgnoreExec',        # The instruction ignores the Exec Mask
@@ -100,6 +105,7 @@
         'NoSegment',         # Does not have an associated segment

         # Coherence flags
+ 'GroupCoherent', # Coherent with other work-items in same workgroup 'GloballyCoherent', # Coherent with other work-items on same device 'SystemCoherent', # Coherent with a different device, or the host

@@ -111,5 +117,10 @@
         # MAC, MAD, FMA
         'FMA',               # FMA
         'MAC',               # MAC
-        'MAD'                # MAD
+        'MAD',               # MAD
+
+        # VALU CAC Group flags
+        'ValuCacGrp0',       # VALU CAC Group 0 (mac, mad, fma, div)
+        'ValuCacGrp1',       # VALU CAC Group 1 (mul)
+        'ValuCacGrp2',       # VALU CAC Group 2 (all others)
         ]
diff --git a/src/gpu-compute/gpu_static_inst.hh b/src/gpu-compute/gpu_static_inst.hh
index ed753c5..6ce0392 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -147,8 +147,8 @@
     bool writesVCC() const { return _flags[WritesVCC]; }
     // Identify instructions that implicitly read the Execute mask
     // as a source operand but not to dictate which threads execute.
-    bool readsEXEC() const { return _flags[ReadsEXEC]; }
-    bool writesEXEC() const { return _flags[WritesEXEC]; }
+    bool readsEXEC() const { return _flags[ReadsExec]; }
+    bool writesEXEC() const { return _flags[WritesExec]; }
     bool readsMode() const { return _flags[ReadsMode]; }
     bool writesMode() const { return _flags[WritesMode]; }
     bool ignoreExec() const { return _flags[IgnoreExec]; }

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I976cbd407a466e8ad77c84dbdc29082f49e28f3b
Gerrit-Change-Number: 47102
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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