Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40910 )
Change subject: arch-power: Add doubleword modulo instructions
......................................................................
arch-power: Add doubleword modulo instructions
This adds the following instructions.
* Modulo Signed Doubleword (modsd)
* Modulo Unsigned Doubleword (modud)
Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40910
Reviewed-by: Boris Shingarov <shinga...@labware.com>
Maintainer: Boris Shingarov <shinga...@labware.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/power/isa/decoder.isa
1 file changed, 42 insertions(+), 18 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 5b16d72..3aa973f 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -335,15 +335,27 @@
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
- 267: IntArithOp::moduw({{
- uint64_t src1 = Ra_uw;
- uint64_t src2 = Rb_uw;
- if (src2 != 0) {
- Rt = src1 % src2;
- } else {
- Rt = 0;
- }
- }});
+ format IntArithOp {
+ 265: modud({{
+ uint64_t src1 = Ra;
+ uint64_t src2 = Rb;
+ if (src2 != 0) {
+ Rt = src1 % src2;
+ } else {
+ Rt = 0;
+ }
+ }});
+
+ 267: moduw({{
+ uint64_t src1 = Ra_uw;
+ uint64_t src2 = Rb_uw;
+ if (src2 != 0) {
+ Rt = src1 % src2;
+ } else {
+ Rt = 0;
+ }
+ }});
+ }
278: MiscOp::dcbt({{ }});
279: LoadIndexOp::lhzx({{ Rt = Mem_uh; }});
@@ -447,15 +459,27 @@
759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
- 779: IntArithOp::modsw({{
- int64_t src1 = Ra_sw;
- int64_t src2 = Rb_sw;
- if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
- Rt = src1 % src2;
- } else {
- Rt = 0;
- }
- }});
+ format IntArithOp {
+ 777: modsd({{
+ int64_t src1 = Ra_sd;
+ int64_t src2 = Rb_sd;
+ if ((src1 != INT64_MIN || src2 != -1) && src2 != 0) {
+ Rt = src1 % src2;
+ } else {
+ Rt = 0;
+ }
+ }});
+
+ 779: modsw({{
+ int64_t src1 = Ra_sw;
+ int64_t src2 = Rb_sw;
+ if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+ Rt = src1 % src2;
+ } else {
+ Rt = 0;
+ }
+ }});
+ }
790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Gerrit-Change-Number: 40910
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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