Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48149 )
Change subject: arch-arm: Provide support for a multilevel-TLB in the ArmMMU
......................................................................
arch-arm: Provide support for a multilevel-TLB in the ArmMMU
This is an initial implementation. It adapts the current MMU code
to account for extra levels of TLBs but it is still missing the
configurability we are looking for (to select the associativity
of the TLB and the replacement policy as an example)
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I938ec38183337cd0e839bf3e3cd03594126128cd
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/tlb.cc
3 files changed, 65 insertions(+), 12 deletions(-)
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 2ed38b5..e04df89 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -1307,6 +1307,22 @@
is_secure, tran_type, stage2 ? s2State : s1State);
}
+TlbEntry*
+MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool hyp, bool secure,
+ bool functional, bool ignore_asn, ExceptionLevel target_el,
+ bool in_host, bool stage2, BaseMMU::Mode mode)
+{
+ TLB *tlb = getTlb(mode, stage2);
+ TlbEntry* te = nullptr;
+ while (!te && tlb) {
+ te = tlb->lookup(va, asid, vmid, hyp, secure, functional,
+ ignore_asn, target_el, in_host, mode);
+ tlb = static_cast<TLB*>(tlb->getNextLevel());
+ }
+
+ return te;
+}
+
Fault
MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode
mode,
Translation *translation, bool timing, bool functional,
@@ -1329,9 +1345,9 @@
vaddr = vaddr_tainted;
}
- auto tlb = getTlb(mode, state.isStage2);
- *te = tlb->lookup(vaddr, state.asid, state.vmid, state.isHyp,
is_secure,
- false, false, target_el, false, mode);
+ *te = lookup(vaddr, state.asid, state.vmid, state.isHyp, is_secure,
false,
+ false, target_el, false, state.isStage2, mode);
+
if (*te == NULL) {
if (req->isPrefetch()) {
// if the request is a prefetch don't attempt to fill the TLB
or go
@@ -1359,10 +1375,8 @@
return fault;
}
- *te = tlb->lookup(vaddr, state.asid, state.vmid, state.isHyp,
is_secure,
- true, false, target_el, false, mode);
- if (!*te)
- tlb->printTlb();
+ *te = lookup(vaddr, state.asid, state.vmid, state.isHyp, is_secure,
+ true, false, target_el, false, state.isStage2, mode);
assert(*te);
}
return NoFault;
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index b11e156..61d9c9e 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -267,8 +267,15 @@
void
flushStage1(const OP &tlbi_op)
{
- iflush(tlbi_op);
- dflush(tlbi_op);
+ for (auto tlb : instruction) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
+ for (auto tlb : data) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
+ for (auto tlb : unified) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
}
template <typename OP>
@@ -283,14 +290,24 @@
void
iflush(const OP &tlbi_op)
{
- getITBPtr()->flush(tlbi_op);
+ for (auto tlb : instruction) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
+ for (auto tlb : unified) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
}
template <typename OP>
void
dflush(const OP &tlbi_op)
{
- getDTBPtr()->flush(tlbi_op);
+ for (auto tlb : data) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
+ for (auto tlb : unified) {
+ static_cast<TLB*>(tlb)->flush(tlbi_op);
+ }
}
void
@@ -323,6 +340,24 @@
static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
public:
+ /** Lookup an entry in the TLB
+ * @param vpn virtual address
+ * @param asn context id/address space id to use
+ * @param vmid The virtual machine ID used for stage 2 translation
+ * @param secure if the lookup is secure
+ * @param hyp if the lookup is done from hyp mode
+ * @param functional if the lookup should modify state
+ * @param ignore_asn if on lookup asn should be ignored
+ * @param target_el selecting the translation regime
+ * @param in_host if we are in host (EL2&0 regime)
+ * @param mode to differentiate between read/writes/fetches.
+ * @return pointer to TLB entry if it exists
+ */
+ TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
+ bool secure, bool functional,
+ bool ignore_asn, ExceptionLevel target_el,
+ bool in_host, bool stage2, BaseMMU::Mode mode);
+
Fault getTE(TlbEntry **te, const RequestPtr &req,
ThreadContext *tc, Mode mode,
Translation *translation, bool timing, bool functional,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d6f92fd..fa82ae7 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -162,7 +162,11 @@
table[size-1].nstid, table[size-1].global,
table[size-1].isHyp,
table[size-1].el);
- //inserting to MRU position and evicting the LRU one
+ // inserting to MRU position and evicting the LRU one
+ // to the next level
+ if (_nextLevel) {
+ static_cast<TLB*>(_nextLevel)->insert(table[size - 1]);
+ }
for (int i = size - 1; i > 0; --i)
table[i] = table[i-1];
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I938ec38183337cd0e839bf3e3cd03594126128cd
Gerrit-Change-Number: 48149
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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