[gem5-dev] Change in gem5/gem5[develop]: cpu,arch-arm: Track register size in RegClassInfo.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49104 )

Change subject: cpu,arch-arm: Track register size in RegClassInfo.
......................................................................

cpu,arch-arm: Track register size in RegClassInfo.

By default, registers are the size of RegVal, the type often used to
store them. For some types of registers, like vector or vector predicate
registers, the size of each individual register is larger, and can't fit
in a primitive type.

To help facilitate storing even these outliers in a generalized way,
this change adds two fields to RegClassInfo to track the size of
individual registers. One tracks the raw size of the registers
themselves, and the other tracks the minimal shift necessary to find the
offset of a register in a contiguous(ish) array of bytes. By forcing
each register to be aligned to a power of two boundary, we avoid having
to do a multiplication to find their address even if the registers are
oddly sized. We can instead do a shift with a precomputed shift amount
which should be faster.

Change-Id: I035f1b4cb00ece4e8306d7953ea358af75a0d1de
---
M src/arch/arm/isa.cc
M src/cpu/reg_class.hh
2 files changed, 13 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 51856ca..bf59227 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -81,9 +81,10 @@
 {
     _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
     _regClasses.emplace_back(0);
-    _regClasses.emplace_back(NumVecRegs);
-    _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
-    _regClasses.emplace_back(NumVecPredRegs);
+    _regClasses.emplace_back(NumVecRegs, -1, sizeof(VecRegContainer));
+    _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg, -1,
+            sizeof(VecElem));
+    _regClasses.emplace_back(NumVecPredRegs, -1,  
sizeof(VecPredRegContainer));
     _regClasses.emplace_back(NUM_CCREGS);
     _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index febaa55..f60f10c 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -46,6 +46,7 @@
 #include <string>

 #include "arch/vecregs.hh"
+#include "base/intmath.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"

@@ -85,13 +86,17 @@
   private:
     size_t _size;
     const RegIndex _zeroReg;
+    size_t _regBytes;
+    size_t _regShift;

     static inline DefaultRegClassOps defaultOps;
     RegClassOps *_ops = &defaultOps;

   public:
-    RegClass(size_t new_size, RegIndex new_zero=-1) :
-        _size(new_size), _zeroReg(new_zero)
+    RegClass(size_t new_size, RegIndex new_zero=-1,
+            size_t reg_bytes=sizeof(RegVal)) :
+        _size(new_size), _zeroReg(new_zero), _regBytes(reg_bytes),
+        _regShift(ceilLog2(reg_bytes))
     {}
     RegClass(size_t new_size, RegClassOps &new_ops, RegIndex new_zero=-1) :
         RegClass(new_size, new_zero)
@@ -101,6 +106,8 @@

     size_t size() const { return _size; }
     RegIndex zeroReg() const { return _zeroReg; }
+    size_t regBytes() const { return _regBytes; }
+    size_t regShift() const { return _regShift; }

     std::string regName(const RegId &id) const { return _ops->regName(id);  
}
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I035f1b4cb00ece4e8306d7953ea358af75a0d1de
Gerrit-Change-Number: 49104
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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