[gem5-dev] Change in gem5/gem5[develop]: arm: Add methods to sync vector regs and vector reg elements.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49145 )

Change subject: arm: Add methods to sync vector regs and vector reg  
elements.
......................................................................

arm: Add methods to sync vector regs and vector reg elements.

If we've been using one and need to start using the other, this will
sync over the most up to date contents from the old one to the new one.

Change-Id: I8443928ac2d8694ee02fe8d2bf17dbf9a04e5a11
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 31 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index ae7213d..a0f7088 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -45,6 +45,7 @@
 #include "arch/arm/page_size.hh"
 #include "arch/arm/regs/cc.hh"
 #include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/vec.hh"
 #include "arch/arm/system.hh"
 #include "base/compiler.hh"
 #include "cpu/base.hh"
@@ -1328,5 +1329,32 @@
     }
 }

+void
+syncVecRegsToElems(ThreadContext *tc)
+{
+    for (int ri = 0; ri < NumVecRegs; ri++) {
+        RegId reg_id(VecRegClass, ri);
+        const VecRegContainer &reg = tc->readVecReg(reg_id);
+        for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+            RegId elem_id(VecElemClass, ri, ei);
+            tc->setVecElem(elem_id, reg.as<VecElem>()[ei]);
+        }
+    }
+}
+
+void
+syncVecElemsToRegs(ThreadContext *tc)
+{
+    for (int ri = 0; ri < NumVecRegs; ri++) {
+        VecRegContainer reg;
+        for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+            RegId elem_id(VecElemClass, ri, ei);
+            reg.as<VecElem>()[ei] = tc->readVecElem(elem_id);
+        }
+        RegId reg_id(VecRegClass, ri);
+        tc->setVecReg(reg_id, reg);
+    }
+}
+
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 13914c2..f298215 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -392,6 +392,9 @@

 bool isUnpriviledgeAccess(ThreadContext *tc);

+void syncVecRegsToElems(ThreadContext *tc);
+void syncVecElemsToRegs(ThreadContext *tc);
+
 } // namespace ArmISA
 } // namespace gem5


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8443928ac2d8694ee02fe8d2bf17dbf9a04e5a11
Gerrit-Change-Number: 49145
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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