Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49145 )
Change subject: arm: Add methods to sync vector regs and vector reg
elements.
......................................................................
arm: Add methods to sync vector regs and vector reg elements.
If we've been using one and need to start using the other, this will
sync over the most up to date contents from the old one to the new one.
Change-Id: I8443928ac2d8694ee02fe8d2bf17dbf9a04e5a11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49145
Reviewed-by: Bobby R. Bruce <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 31 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index b716ba9..c4331a4 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -45,6 +45,7 @@
#include "arch/arm/page_size.hh"
#include "arch/arm/regs/cc.hh"
#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/vec.hh"
#include "arch/arm/system.hh"
#include "base/compiler.hh"
#include "cpu/base.hh"
@@ -1327,5 +1328,32 @@
}
}
+void
+syncVecRegsToElems(ThreadContext *tc)
+{
+ for (int ri = 0; ri < NumVecRegs; ri++) {
+ RegId reg_id(VecRegClass, ri);
+ const VecRegContainer ® = tc->readVecReg(reg_id);
+ for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+ RegId elem_id(VecElemClass, ri, ei);
+ tc->setVecElem(elem_id, reg.as<VecElem>()[ei]);
+ }
+ }
+}
+
+void
+syncVecElemsToRegs(ThreadContext *tc)
+{
+ for (int ri = 0; ri < NumVecRegs; ri++) {
+ VecRegContainer reg;
+ for (int ei = 0; ei < NumVecElemPerVecReg; ei++) {
+ RegId elem_id(VecElemClass, ri, ei);
+ reg.as<VecElem>()[ei] = tc->readVecElem(elem_id);
+ }
+ RegId reg_id(VecRegClass, ri);
+ tc->setVecReg(reg_id, reg);
+ }
+}
+
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 9667d47..7d9affa 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -393,6 +393,9 @@
bool isUnpriviledgeAccess(ThreadContext *tc);
+void syncVecRegsToElems(ThreadContext *tc);
+void syncVecElemsToRegs(ThreadContext *tc);
+
} // namespace ArmISA
} // namespace gem5
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8443928ac2d8694ee02fe8d2bf17dbf9a04e5a11
Gerrit-Change-Number: 49145
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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