[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Print vec and vec pred reg values with valString.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49705 )

Change subject: cpu-o3: Print vec and vec pred reg values with valString.
......................................................................

cpu-o3: Print vec and vec pred reg values with valString.

Remove the need for the VecRegContainer and VecPredRegContainer types.

Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63
---
M src/cpu/o3/regfile.hh
1 file changed, 8 insertions(+), 5 deletions(-)



diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index ed15c57..4166a61 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -81,9 +81,12 @@
         const size_t _regBytes;

       public:
+        const RegClass &regClass;
+
         RegFile(const RegClass &info, unsigned num_phys) :
             data(num_phys << info.regShift()), _size(num_phys),
-            _regShift(info.regShift()), _regBytes(info.regBytes())
+            _regShift(info.regShift()), _regBytes(info.regBytes()),
+            regClass(info)
         {}

         size_t size() const { return _size; }
@@ -269,7 +272,7 @@
           case VecRegClass:
             vectorRegFile.get(idx, val);
             DPRINTF(IEW, "RegFile: Access to vector register %i, has "
-                    "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+                    "data %s\n", idx,  
vectorRegFile.regClass.valString(val));
             break;
           case VecElemClass:
             *(RegVal *)val = getReg(phys_reg);
@@ -277,7 +280,7 @@
           case VecPredRegClass:
             vecPredRegFile.get(idx, val);
             DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
-                    "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+                    "data %s\n", idx,  
vecPredRegFile.regClass.valString(val));
             break;
           case CCRegClass:
             *(RegVal *)val = getReg(phys_reg);
@@ -351,7 +354,7 @@
             break;
           case VecRegClass:
             DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
-                    idx, *(TheISA::VecRegContainer *)val);
+                    idx, vectorRegFile.regClass.valString(val));
             vectorRegFile.set(idx, val);
             break;
           case VecElemClass:
@@ -359,7 +362,7 @@
             break;
           case VecPredRegClass:
             DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-                    idx, *(TheISA::VecRegContainer *)val);
+                    idx, vectorRegFile.regClass.valString(val));
             vecPredRegFile.set(idx, val);
             break;
           case CCRegClass:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63
Gerrit-Change-Number: 49705
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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