Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49705 )
(
50 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: cpu-o3: Print vec and vec pred reg values with valString.
......................................................................
cpu-o3: Print vec and vec pred reg values with valString.
Remove the need for the VecRegContainer and VecPredRegContainer types.
Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49705
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/o3/regfile.hh
1 file changed, 19 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 9cb8fc2..b5d972d 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -211,7 +211,7 @@
case VecRegClass:
vectorRegFile.get(idx, val);
DPRINTF(IEW, "RegFile: Access to vector register %i, has "
- "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+ "data %s\n", idx,
vectorRegFile.regClass.valString(val));
break;
case VecElemClass:
*(RegVal *)val = getReg(phys_reg);
@@ -219,7 +219,7 @@
case VecPredRegClass:
vecPredRegFile.get(idx, val);
DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
- "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+ "data %s\n", idx,
vecPredRegFile.regClass.valString(val));
break;
case CCRegClass:
*(RegVal *)val = getReg(phys_reg);
@@ -293,7 +293,7 @@
break;
case VecRegClass:
DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
- idx, *(TheISA::VecRegContainer *)val);
+ idx, vectorRegFile.regClass.valString(val));
vectorRegFile.set(idx, val);
break;
case VecElemClass:
@@ -301,7 +301,7 @@
break;
case VecPredRegClass:
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
- idx, *(TheISA::VecRegContainer *)val);
+ idx, vectorRegFile.regClass.valString(val));
vecPredRegFile.set(idx, val);
break;
case CCRegClass:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63
Gerrit-Change-Number: 49705
Gerrit-PatchSet: 53
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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