Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49749 )
Change subject: arch: Remove plumbing for operand predication.
......................................................................
arch: Remove plumbing for operand predication.
The operand predication mechanism has been replaced by mapping
predicate-false register reads/writes to InvalidRegClass.
Change-Id: I57e7aadb7a0d682c225f6a5fe673cba8ddf1c4f8
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/isa_parser.py
M src/arch/isa_parser/operand_list.py
M src/arch/isa_parser/operand_types.py
M src/arch/x86/isa/operands.isa
5 files changed, 47 insertions(+), 94 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 5c916b0..31c6f34 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -110,11 +110,11 @@
class IntReg(IntRegNPC):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ({self.reg_spec} == PCReg) ? ' \
f'readPC(xc) : xc->getRegOperand(this, {op_idx});\n'
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
if ({self.reg_spec} == PCReg)
setNextPC(xc, {self.base_name});
@@ -130,14 +130,14 @@
class IntRegAPC(IntReg):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ({self.reg_spec} == PCReg) ? ' \
f'(roundDown(readPC(xc), 4)) : ' \
f'xc->getRegOperand(this, {op_idx});\n'
class IntRegIWPC(IntReg):
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
if ({self.reg_spec} == PCReg)
setIWNextPC(xc, {self.base_name});
@@ -149,7 +149,7 @@
class IntRegAIWPC(IntReg):
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
if ({self.reg_spec} == PCReg) {"{"}
if ((bool)THUMB)
@@ -169,11 +169,11 @@
return f'(({self.reg_spec}) == gem5::ArmISA::INTREG_ZERO) ? ' \
f'RegId() : RegId({self.reg_class}, {self.reg_spec})'
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {op_idx})) &
mask(intWidth);\n'
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
xc->setRegOperand(this, {op_idx}, {self.base_name} &
mask(intWidth));
@@ -185,12 +185,12 @@
class IntRegX64(IntReg64):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {op_idx}) & ' \
'mask(aarch64 ? 64 : 32));\n'
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
xc->setRegOperand(this, {op_idx}, {self.base_name} &
mask(aarch64 ? 64 : 32));
@@ -200,11 +200,11 @@
class IntRegW64(IntReg64):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {op_idx})) & mask(32);\n'
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
xc->setRegOperand(this, {op_idx}, {self.base_name} & mask(32));
if (traceData)
@@ -221,11 +221,11 @@
class CntrlNsBankedReg(CntrlReg):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = ' \
f'xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()));\n'
@overrideInOperand
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return f'''
xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()),
{self.base_name});
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index c730d80..4e79901 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -125,17 +125,6 @@
if operands.readPC or operands.setPC:
myDict['op_decl'] += 'TheISA::PCState
__parserAutoPCState;\n'
- # In case there are predicated register reads and write,
declare
- # the variables for register indicies. It is being assumed that
- # all the operands in the OperandList are also in the
- # SubOperandList and in the same order. Otherwise, it is
- # expected that predication would not be used for the operands.
- if operands.predRead:
- myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n'
- if operands.predWrite:
- myDict['op_decl'] += \
- '[[maybe_unused]] uint8_t _destIndex = 0;\n'
-
is_src = lambda op: op.is_src
is_dest = lambda op: op.is_dest
diff --git a/src/arch/isa_parser/operand_list.py
b/src/arch/isa_parser/operand_list.py
index c26fdf3..3438777 100755
--- a/src/arch/isa_parser/operand_list.py
+++ b/src/arch/isa_parser/operand_list.py
@@ -122,15 +122,10 @@
self.memOperand = mem[0] if mem else None
- # Flags to keep track if one or more operands are to be
read/written
- # conditionally.
- self.predRead = any(i.hasReadPred() for i in self.items)
- self.predWrite = any(i.hasWritePred() for i in self.items)
-
# now make a final pass to finalize op_desc fields that may depend
# on the register enumeration
for op_desc in self.items:
- op_desc.finalize(self.predRead, self.predWrite)
+ op_desc.finalize()
def __len__(self):
return len(self.items)
@@ -235,8 +230,3 @@
self.pcPart = None
if part: self.pcPart = True
if whole: self.pcPart = False
-
- # Flags to keep track if one or more operands are to be
read/written
- # conditionally.
- self.predRead = any(i.hasReadPred() for i in self.items)
- self.predWrite = any(i.hasWritePred() for i in self.items)
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index e22358f..f38fb51 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -45,7 +45,7 @@
class OperandDesc(object):
def __init__(self, base_cls_name, dflt_ext, reg_spec, flags=None,
- sort_pri=None, read_predicate=None, write_predicate=None):
+ sort_pri=None):
from .isa_parser import makeList
@@ -96,8 +96,6 @@
'reg_spec': reg_spec,
'flags': flags,
'sort_pri': sort_pri,
- 'read_predicate': read_predicate,
- 'write_predicate': write_predicate,
})
self.attrs = attrs
@@ -146,32 +144,28 @@
# time of __init__(). The register index enumeration is affected
# by predicated register reads/writes. Hence, we forward the flags
# that indicate whether or not predication is in use.
- def finalize(self, predRead, predWrite):
+ def finalize(self):
self.flags = self.getFlags()
- self.constructor = self.makeConstructor(predRead, predWrite)
+ self.constructor = self.makeConstructor()
self.op_decl = self.makeDecl()
if self.is_src:
- if predRead:
- op_idx = '_sourceIndex++'
- elif hasattr(self, 'src_reg_idx'):
+ if hasattr(self, 'src_reg_idx'):
op_idx = str(self.src_reg_idx)
else:
op_idx = None
- self.op_rd = self.makeRead(predRead, op_idx)
+ self.op_rd = self.makeRead(op_idx)
self.op_src_decl = self.makeDecl()
else:
self.op_rd = ''
self.op_src_decl = ''
if self.is_dest:
- if predRead:
- op_idx = '_destIndex++'
- elif hasattr(self, 'dest_reg_idx'):
+ if hasattr(self, 'dest_reg_idx'):
op_idx = str(self.dest_reg_idx)
else:
op_idx = None
- self.op_wb = self.makeWrite(predWrite, op_idx)
+ self.op_wb = self.makeWrite(op_idx)
self.op_dest_decl = self.makeDecl()
else:
self.op_wb = ''
@@ -189,12 +183,6 @@
def isPCPart(self):
return self.isPCState() and self.reg_spec
- def hasReadPred(self):
- return self.read_predicate != None
-
- def hasWritePred(self):
- return self.write_predicate != None
-
def getFlags(self):
# note the empty slice '[:]' gives us a copy of self.flags[0]
# instead of a reference to it
@@ -214,27 +202,21 @@
def isReg(self):
return 1
- def makeConstructor(self, predRead, predWrite):
+ def makeConstructor(self):
c_src = ''
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % self.srcRegId()
- if self.hasReadPred():
- c_src = '\n\tif (%s) {%s\n\t}' % \
- (self.read_predicate, c_src)
if self.is_dest:
c_dest = self.dst_reg_constructor % self.destRegId()
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
- if self.hasWritePred():
- c_dest = '\n\tif (%s) {%s\n\t}' % \
- (self.write_predicate, c_dest)
return c_src + c_dest
class RegOperand(BaseRegOperand):
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
reg_val = f'xc->getRegOperand(this, {op_idx})'
if self.ctype == 'float':
@@ -242,12 +224,9 @@
elif self.ctype == 'double':
reg_val = f'bitsToFloat64({reg_val})'
- if predRead and self.hasReadPred():
- reg_val = f'({self.read_predicate}) ? {reg_val} : 0'
-
return f'{self.base_name} = {reg_val};\n'
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
reg_val = self.base_name
if self.ctype == 'float':
@@ -255,13 +234,8 @@
elif self.ctype == 'double':
reg_val = f'floatToBits64({reg_val})'
- if predWrite and self.hasWritePred():
- wcond = f'if ({self.write_predicate})'
- else:
- wcond = ''
return f'''
- {wcond}
{{
RegVal final_val = {reg_val};
xc->setRegOperand(this, {op_idx}, final_val);
@@ -335,7 +309,7 @@
(ctype, elem_name, self.base_name, elem_spec)
return c_read
- def makeReadW(self, predWrite, op_idx):
+ def makeReadW(self, op_idx):
c_readw = f'\t\tauto &tmp_d{op_idx} = \n' \
f'\t\t *({self.parser.namespace}::VecRegContainer
*)\n' \
f'\t\t xc->getWritableRegOperand(this, {op_idx});\n'
@@ -365,7 +339,7 @@
(elem_name, name, elem_spec)
return c_read
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
name = self.base_name
if self.is_dest and self.is_src:
name += '_merger'
@@ -387,7 +361,7 @@
c_read += self.makeReadElem(elem, name)
return c_read
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
wb = '''
if (traceData) {
traceData->setData(tmp_d%s);
@@ -395,11 +369,11 @@
''' % op_idx
return wb
- def finalize(self, predRead, predWrite):
- super(VecRegOperand, self).finalize(predRead, predWrite)
+ def finalize(self):
+ super(VecRegOperand, self).finalize()
if self.is_dest:
op_idx = str(self.dest_reg_idx)
- self.op_rd = self.makeReadW(predWrite, op_idx) + self.op_rd
+ self.op_rd = self.makeReadW(op_idx) + self.op_rd
class VecRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
@@ -412,7 +386,7 @@
def makeDecl(self):
return ''
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
c_read = f'\t\t{self.parser.namespace}::VecPredRegContainer ' \
f'\t\t tmp_s{op_idx}; ' \
f'xc->getRegOperand(this, {op_idx}, &tmp_s{op_idx});\n'
@@ -422,7 +396,7 @@
f'{self.parser.operandTypeMap[self.ext]}>();\n'
return c_read
- def makeReadW(self, predWrite, op_idx):
+ def makeReadW(self, op_idx):
c_readw = f'\t\tauto &tmp_d{op_idx} = \n' \
f'\t\t *({self.parser.namespace}::' \
f'VecPredRegContainer *)xc->getWritableRegOperand(' \
@@ -433,7 +407,7 @@
self.parser.operandTypeMap[self.ext])
return c_readw
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
wb = '''
if (traceData) {
traceData->setData(tmp_d%s);
@@ -441,11 +415,11 @@
''' % op_idx
return wb
- def finalize(self, predRead, predWrite):
- super(VecPredRegOperand, self).finalize(predRead, predWrite)
+ def finalize(self):
+ super(VecPredRegOperand, self).finalize()
if self.is_dest:
op_idx = str(self.dest_reg_idx)
- self.op_rd = self.makeReadW(predWrite, op_idx) + self.op_rd
+ self.op_rd = self.makeReadW(op_idx) + self.op_rd
class VecPredRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
@@ -461,7 +435,7 @@
def isControlReg(self):
return 1
- def makeConstructor(self, predRead, predWrite):
+ def makeConstructor(self):
c_src = ''
c_dest = ''
@@ -473,7 +447,7 @@
return c_src + c_dest
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read control register as FP')
@@ -481,7 +455,7 @@
return '%s = xc->readMiscRegOperand(this, %s);\n' % \
(self.base_name, op_idx)
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to write control register as FP')
wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
@@ -500,17 +474,17 @@
def isMem(self):
return 1
- def makeConstructor(self, predRead, predWrite):
+ def makeConstructor(self):
return ''
def makeDecl(self):
# Declare memory data variable.
return '%s %s = {};\n' % (self.ctype, self.base_name)
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return ''
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
return ''
class MemOperandDesc(OperandDesc):
@@ -518,10 +492,10 @@
super(MemOperandDesc, self).__init__('Mem', *args, **kwargs)
class PCStateOperand(Operand):
- def makeConstructor(self, predRead, predWrite):
+ def makeConstructor(self):
return ''
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
if self.reg_spec:
# A component of the PC state.
return '%s = __parserAutoPCState.%s();\n' % \
@@ -530,7 +504,7 @@
# The whole PC state itself.
return '%s = xc->pcState();\n' % self.base_name
- def makeWrite(self, predWrite, op_idx):
+ def makeWrite(self, op_idx):
if self.reg_spec:
# A component of the PC state.
return '__parserAutoPCState.%s(%s);\n' % \
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index a30bdef..4e61011 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -66,7 +66,7 @@
class PickedReg(IntReg):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = pick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
@@ -76,7 +76,7 @@
class SignedPickedReg(IntReg):
@overrideInOperand
- def makeRead(self, predRead, op_idx):
+ def makeRead(self, op_idx):
return f'{self.base_name} = signedPick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I57e7aadb7a0d682c225f6a5fe673cba8ddf1c4f8
Gerrit-Change-Number: 49749
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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