Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49746 )
Change subject: arch,cpu: Remove the idea of a zero register.
......................................................................
arch,cpu: Remove the idea of a zero register.
This is now handled by using the InvalidRegClass.
Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
---
M src/arch/arm/isa.cc
M src/arch/mips/isa.cc
M src/arch/power/isa.cc
M src/arch/riscv/isa.cc
M src/arch/sparc/isa.cc
M src/arch/x86/isa.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/execute.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/scoreboard.cc
M src/cpu/o3/scoreboard.hh
M src/cpu/reg_class.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple_thread.hh
29 files changed, 42 insertions(+), 121 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4fea073..0f946b5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -88,14 +88,14 @@
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
- _regClasses.emplace_back(NUM_INTREGS, debug::IntRegs, INTREG_ZERO);
+ _regClasses.emplace_back(NUM_INTREGS, debug::IntRegs);
_regClasses.emplace_back(0, debug::FloatRegs);
- _regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
-1,
+ _regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
sizeof(VecRegContainer));
_regClasses.emplace_back(NumVecRegs * ArmISA::NumVecElemPerVecReg,
vecRegElemClassOps, debug::VecRegs);
_regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps,
- debug::VecPredRegs, -1, sizeof(VecPredRegContainer));
+ debug::VecPredRegs, sizeof(VecPredRegContainer));
_regClasses.emplace_back(NUM_CCREGS, debug::CCRegs);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps,
debug::MiscRegs);
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 66348a4..683ed72 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -100,7 +100,7 @@
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
- _regClasses.emplace_back(NumIntRegs, debug::IntRegs, 0);
+ _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to MIPS.
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 4cf7b39..d28894d 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -54,7 +54,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(NumIntRegs, debug::IntRegs, NumIntRegs - 1);
+ _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs);
_regClasses.emplace_back(2, debug::IntRegs);
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 522686a..3a566f5 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -187,7 +187,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(NumIntRegs, debug::IntRegs, 0);
+ _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index e360d74..0c4ddcd 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -70,7 +70,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(NumIntRegs, debug::IntRegs, 0);
+ _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for
SPARC
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable for
SPARC
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index fd65470..f8e3a43 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -146,7 +146,7 @@
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
- _regClasses.emplace_back(NumIntRegs, debug::IntRegs, INTREG_T0);
+ _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to X86
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to X86
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index c20321c..9434c9a 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -64,7 +64,6 @@
CheckerCPU::CheckerCPU(const Params &p)
: BaseCPU(p, true),
- zeroReg(params().isa[0]->regClasses().at(IntRegClass).zeroReg()),
systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
tc(NULL), thread(NULL),
unverifiedReq(nullptr),
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 16d9d58..273dc5e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -87,8 +87,6 @@
/** id attached to all issued requests */
RequestorID requestorId;
- const RegIndex zeroReg;
-
public:
void init() override;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 3ccd176..5231802 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -203,9 +203,6 @@
Fault fault = NoFault;
- // maintain $r0 semantics
- thread->setIntReg(zeroReg, 0);
-
// Check if any recent PC changes match up with anything we
// expect to happen. This is mostly to check if traps or
// PC-based events have occurred in both the checker and CPU.
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index b3fed0f..0c87732 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -163,11 +163,7 @@
os << reg_class.regName(reg);
break;
case IntRegClass:
- if (reg.index() == reg_class.zeroReg()) {
- os << 'z';
- } else {
- os << 'r' << reg.index();
- }
+ os << 'r' << reg.index();
break;
case CCRegClass:
os << 'c' << reg.index();
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 3f022fb..35db10c 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -87,7 +87,7 @@
ExecContext (
MinorCPU &cpu_,
SimpleThread &thread_, Execute &execute_,
- MinorDynInstPtr inst_, RegIndex zeroReg) :
+ MinorDynInstPtr inst_) :
cpu(cpu_),
thread(thread_),
execute(execute_),
@@ -97,7 +97,6 @@
pcState(inst->pc);
setPredicate(inst->readPredicate());
setMemAccPredicate(inst->readMemAccPredicate());
- thread.setIntReg(zeroReg, 0);
}
~ExecContext()
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 3234de5..0172c2b 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -70,8 +70,6 @@
inp(inp_),
out(out_),
cpu(cpu_),
- zeroReg(cpu.threads[0]->getIsaPtr()->regClasses().
- at(IntRegClass).zeroReg()),
issueLimit(params.executeIssueLimit),
memoryIssueLimit(params.executeMemoryIssueLimit),
commitLimit(params.executeCommitLimit),
@@ -90,8 +88,7 @@
params.executeLSQRequestsQueueSize,
params.executeLSQTransfersQueueSize,
params.executeLSQStoreBufferSize,
- params.executeLSQMaxStoreBufferStoresPerCycle,
- zeroReg),
+ params.executeLSQMaxStoreBufferStoresPerCycle),
executeInfo(params.numThreads,
ExecuteThreadInfo(params.executeCommitLimit)),
interruptPriority(0),
@@ -330,7 +327,7 @@
ThreadID thread_id = inst->id.threadId;
ThreadContext *thread = cpu.getContext(thread_id);
- ExecContext context(cpu, *cpu.threads[thread_id], *this, inst,
zeroReg);
+ ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
PacketPtr packet = response->packet;
@@ -465,8 +462,7 @@
ThreadContext *thread = cpu.getContext(inst->id.threadId);
TheISA::PCState old_pc = thread->pcState();
- ExecContext context(cpu, *cpu.threads[inst->id.threadId],
- *this, inst, zeroReg);
+ ExecContext context(cpu, *cpu.threads[inst->id.threadId], *this,
inst);
DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst);
@@ -912,8 +908,7 @@
panic("We should never hit the case where we try to commit from a "
"suspended thread as the streamSeqNum should not match");
} else if (inst->isFault()) {
- ExecContext context(cpu, *cpu.threads[thread_id], *this,
- inst, zeroReg);
+ ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n",
inst->fault->name());
@@ -974,8 +969,7 @@
* backwards, so no other branches may evaluate this cycle*/
completed_inst = false;
} else {
- ExecContext context(cpu, *cpu.threads[thread_id], *this,
- inst, zeroReg);
+ ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
DPRINTF(MinorExecute, "Committing inst: %s\n", *inst);
diff --git a/src/cpu/minor/execute.hh b/src/cpu/minor/execute.hh
index 56966ba..f74d0d7 100644
--- a/src/cpu/minor/execute.hh
+++ b/src/cpu/minor/execute.hh
@@ -78,9 +78,6 @@
/** Pointer back to the containing CPU */
MinorCPU &cpu;
- /** Index of the zero integer register. */
- const RegIndex zeroReg;
-
/** Number of instructions that can be issued per cycle */
unsigned int issueLimit;
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 1b2d7dd..8c21890 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -59,10 +59,9 @@
{
LSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool
isLoad_,
- RegIndex zero_reg, PacketDataPtr data_, uint64_t *res_) :
+ PacketDataPtr data_, uint64_t *res_) :
SenderState(),
port(port_),
- zeroReg(zero_reg),
inst(inst_),
isLoad(isLoad_),
data(data_),
@@ -82,7 +81,7 @@
{
SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
TheISA::PCState old_pc = thread.pcState();
- ExecContext context(port.cpu, thread, port.execute, inst, zeroReg);
+ ExecContext context(port.cpu, thread, port.execute, inst);
[[maybe_unused]] Fault fault = inst->translationFault;
// Give the instruction a chance to suppress a translation fault
@@ -105,7 +104,7 @@
SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
TheISA::PCState old_pc = thread.pcState();
- ExecContext context(port.cpu, thread, port.execute, inst, zeroReg);
+ ExecContext context(port.cpu, thread, port.execute, inst);
context.setMemAccPredicate(false);
inst->staticInst->completeAcc(nullptr, &context, inst->traceData);
@@ -394,7 +393,7 @@
LSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
bool isLoad_, PacketDataPtr data_, uint64_t *res_) :
- LSQRequest(port_, inst_, isLoad_, port_.zeroReg, data_, res_),
+ LSQRequest(port_, inst_, isLoad_, data_, res_),
translationEvent([this]{ sendNextFragmentToTranslation(); },
"translationEvent"),
numFragments(0),
@@ -1133,7 +1132,7 @@
SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
TheISA::PCState old_pc = thread.pcState();
- ExecContext context(cpu, thread, execute, request->inst, zeroReg);
+ ExecContext context(cpu, thread, execute, request->inst);
/* Handle LLSC requests and tests */
if (is_load) {
@@ -1407,12 +1406,10 @@
unsigned int in_memory_system_limit, unsigned int line_width,
unsigned int requests_queue_size, unsigned int transfers_queue_size,
unsigned int store_buffer_size,
- unsigned int store_buffer_cycle_store_limit,
- RegIndex zero_reg) :
+ unsigned int store_buffer_cycle_store_limit) :
Named(name_),
cpu(cpu_),
execute(execute_),
- zeroReg(zero_reg),
dcachePort(dcache_port_name_, *this, cpu_),
lastMemBarrier(cpu.numThreads, 0),
state(MemoryRunning),
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 40e95e2..4a95bf7 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -72,8 +72,6 @@
MinorCPU &cpu;
Execute &execute;
- const RegIndex zeroReg;
-
protected:
/** State of memory access for head access. */
enum MemoryState
@@ -134,8 +132,6 @@
/** Owning port */
LSQ &port;
- const RegIndex zeroReg;
-
/** Instruction which made this request */
MinorDynInstPtr inst;
@@ -208,8 +204,7 @@
public:
LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
- RegIndex zero_reg, PacketDataPtr data_ = NULL,
- uint64_t *res_ = NULL);
+ PacketDataPtr data_ = NULL, uint64_t *res_ = NULL);
virtual ~LSQRequest();
@@ -319,7 +314,7 @@
public:
SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
/* Say this is a load, not actually relevant */
- LSQRequest(port_, inst_, true, port_.zeroReg, NULL, 0)
+ LSQRequest(port_, inst_, true, NULL, 0)
{ }
};
@@ -386,7 +381,7 @@
public:
SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_,
bool isLoad_, PacketDataPtr data_ = NULL, uint64_t *res_ =
NULL) :
- LSQRequest(port_, inst_, isLoad_, port_.zeroReg, data_, res_),
+ LSQRequest(port_, inst_, isLoad_, data_, res_),
packetInFlight(false),
packetSent(false)
{ }
@@ -656,8 +651,7 @@
unsigned int max_accesses_in_memory_system, unsigned int
line_width,
unsigned int requests_queue_size, unsigned int
transfers_queue_size,
unsigned int store_buffer_size,
- unsigned int store_buffer_cycle_store_limit,
- RegIndex zero_reg);
+ unsigned int store_buffer_cycle_store_limit);
virtual ~LSQ();
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index a928444..18e1f5a 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -82,8 +82,6 @@
* [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
const unsigned numRegs;
- const RegIndex zeroReg;
-
/** Type to use when indexing numResults */
typedef unsigned short int Index;
@@ -118,7 +116,6 @@
vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).size()),
vecPredRegOffset(vecRegOffset +
reg_classes.at(VecElemClass).size()),
numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass).size()),
- zeroReg(reg_classes.at(IntRegClass).zeroReg()),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, 0),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bf15214..954ca30 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -98,8 +98,7 @@
rob(this, params),
- scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs(),
- params.isa[0]->regClasses().at(IntRegClass).zeroReg()),
+ scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs()),
isa(numThreads, NULL),
diff --git a/src/cpu/o3/probe/elastic_trace.cc
b/src/cpu/o3/probe/elastic_trace.cc
index 422f69a..ca40bc3 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -65,9 +65,6 @@
stats(this)
{
cpu = dynamic_cast<CPU *>(params.manager);
- const BaseISA::RegClasses ®Classes =
- cpu->getContext(0)->getIsaPtr()->regClasses();
- zeroReg = regClasses.at(IntRegClass).zeroReg();
fatal_if(!cpu, "Manager of %s is not of type O3CPU and thus does not "\
"support dependency tracing.\n", name());
@@ -251,9 +248,7 @@
for (int src_idx = 0; src_idx < max_regs; src_idx++) {
const RegId& src_reg = dyn_inst->srcRegIdx(src_idx);
- if (!src_reg.is(MiscRegClass) &&
- !((src_reg.is(IntRegClass) && src_reg.index() == zeroReg) |
|
- src_reg.is(InvalidRegClass))) {
+ if (!src_reg.is(MiscRegClass) && !src_reg.is(InvalidRegClass)) {
// Get the physical register index of the i'th source register.
PhysRegIdPtr phys_src_reg =
dyn_inst->regs.renamedSrcIdx(src_idx);
DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg"
@@ -284,9 +279,7 @@
// For data dependency tracking the register must be an int, float
or
// CC register and not a Misc register.
const RegId& dest_reg = dyn_inst->destRegIdx(dest_idx);
- if (!dest_reg.is(MiscRegClass) &&
- !((dest_reg.is(IntRegClass) && dest_reg.index() ==
zeroReg) ||
- dest_reg.is(InvalidRegClass))) {
+ if (!dest_reg.is(MiscRegClass) && !dest_reg.is(InvalidRegClass)) {
// Get the physical register index of the i'th destination
// register.
PhysRegIdPtr phys_dest_reg =
diff --git a/src/cpu/o3/probe/elastic_trace.hh
b/src/cpu/o3/probe/elastic_trace.hh
index 53a6cbe..bf72f1d 100644
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -190,8 +190,6 @@
*/
bool firstWin;
- RegIndex zeroReg;
-
/**
* @defgroup InstExecInfo Struct for storing information before an
* instruction reaches the commit stage, e.g. execute timestamp.
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 8e5d418..1a20fe9 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -86,8 +86,6 @@
intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
}
- zeroReg = RegId(IntRegClass, reg_classes.at(IntRegClass).zeroReg());
-
// The next batch of the registers are the floating-point physical
// registers; put them onto the floating-point free list.
for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index f402c23..ae794e5 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -137,7 +137,6 @@
/** Integer register file. */
RegFile intRegFile;
std::vector<PhysRegId> intRegIds;
- RegId zeroReg;
/** Floating point register file. */
RegFile floatRegFile;
@@ -316,8 +315,7 @@
case InvalidRegClass:
break;
case IntRegClass:
- if (phys_reg->index() != zeroReg.index())
- intRegFile.reg(idx) = val;
+ intRegFile.reg(idx) = val;
DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
idx, val);
break;
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 4219e72..4b3a010 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -54,8 +54,7 @@
namespace o3
{
-SimpleRenameMap::SimpleRenameMap()
- : freeList(NULL), zeroReg(IntRegClass, 0)
+SimpleRenameMap::SimpleRenameMap() : freeList(NULL)
{
}
@@ -68,7 +67,6 @@
map.resize(reg_class.size());
freeList = _freeList;
- zeroReg = RegId(IntRegClass, reg_class.zeroReg());
}
SimpleRenameMap::RenameInfo
@@ -79,10 +77,7 @@
// requested architected register.
PhysRegIdPtr prev_reg = map[arch_reg.index()];
- if (arch_reg == zeroReg) {
- assert(prev_reg->index() == zeroReg.index());
- renamed_reg = prev_reg;
- } else if (arch_reg.is(InvalidRegClass)) {
+ if (arch_reg.is(InvalidRegClass)) {
assert(prev_reg->is(InvalidRegClass));
renamed_reg = prev_reg;
} else if (prev_reg->getNumPinnedWrites() > 0) {
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 32af51d..092f06a 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -84,15 +84,6 @@
*/
SimpleFreeList *freeList;
- /**
- * The architectural index of the zero register. This register is
- * mapped but read-only, so we ignore attempts to rename it via
- * the rename() method. If there is no such register for this map
- * table, it should be set to an invalid index so that it never
- * matches.
- */
- RegId zeroReg;
-
public:
SimpleRenameMap();
diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index 5e9fc8b..c4c8bb2 100644
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -35,9 +35,9 @@
namespace o3
{
-Scoreboard::Scoreboard(const std::string &_my_name, unsigned
_numPhysicalRegs,
- RegIndex zero_reg) :
- _name(_my_name), zeroReg(zero_reg), regScoreBoard(_numPhysicalRegs,
true),
+Scoreboard::Scoreboard(const std::string &_my_name,
+ unsigned _numPhysicalRegs) :
+ _name(_my_name), regScoreBoard(_numPhysicalRegs, true),
numPhysRegs(_numPhysicalRegs)
{}
diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh
index f02e53d..d7394f0 100644
--- a/src/cpu/o3/scoreboard.hh
+++ b/src/cpu/o3/scoreboard.hh
@@ -57,9 +57,6 @@
* explicitly because Scoreboard is not a SimObject. */
const std::string _name;
- /** Index of the zero integer register. */
- const RegIndex zeroReg;
-
/** Scoreboard of physical integer registers, saying whether or not
they
* are ready. */
std::vector<bool> regScoreBoard;
@@ -72,8 +69,7 @@
* @param _numPhysicalRegs Number of physical registers.
* @param _numMiscRegs Number of miscellaneous registers.
*/
- Scoreboard(const std::string &_my_name, unsigned _numPhysicalRegs,
- RegIndex _zero_reg);
+ Scoreboard(const std::string &_my_name, unsigned _numPhysicalRegs);
/** Destructor. */
~Scoreboard() {}
@@ -92,11 +88,6 @@
assert(phys_reg->flatIndex() < numPhysRegs);
- bool ready = regScoreBoard[phys_reg->flatIndex()];
-
- if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
- assert(ready);
-
return regScoreBoard[phys_reg->flatIndex()];
}
@@ -130,10 +121,6 @@
assert(phys_reg->flatIndex() < numPhysRegs);
- // zero reg should never be marked unready
- if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
- return;
-
regScoreBoard[phys_reg->flatIndex()] = false;
}
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 02ed4d8..5a7a124 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -82,7 +82,6 @@
{
private:
size_t _size;
- const RegIndex _zeroReg;
size_t _regBytes;
// This is how much to shift an index by to get an offset of a
register in
// a register file from the register index, which would otherwise need
to
@@ -95,20 +94,18 @@
public:
RegClass(size_t new_size, const debug::Flag &debug_flag,
- RegIndex new_zero=-1, size_t reg_bytes=sizeof(RegVal)) :
- _size(new_size), _zeroReg(new_zero), _regBytes(reg_bytes),
- _regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
+ size_t reg_bytes=sizeof(RegVal)) :
+ _size(new_size), _regBytes(reg_bytes),
_regShift(ceilLog2(reg_bytes)),
+ debugFlag(debug_flag)
{}
RegClass(size_t new_size, RegClassOps &new_ops,
- const debug::Flag &debug_flag, RegIndex new_zero=-1,
- size_t reg_bytes=sizeof(RegVal)) :
- RegClass(new_size, debug_flag, new_zero, reg_bytes)
+ const debug::Flag &debug_flag, size_t
reg_bytes=sizeof(RegVal)) :
+ RegClass(new_size, debug_flag, reg_bytes)
{
_ops = &new_ops;
}
size_t size() const { return _size; }
- RegIndex zeroReg() const { return _zeroReg; }
size_t regBytes() const { return _regBytes; }
size_t regShift() const { return _regShift; }
const debug::Flag &debug() const { return debugFlag; }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 76ed9c5..e6262e4 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -84,7 +84,6 @@
: BaseCPU(p),
curThread(0),
branchPred(p.branchPred),
- zeroReg(p.isa[0]->regClasses().at(IntRegClass).zeroReg()),
traceData(NULL),
_status(Idle)
{
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4e94e5c..5e739db 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -83,8 +83,6 @@
ThreadID curThread;
branch_prediction::BPredUnit *branchPred;
- const RegIndex zeroReg;
-
void checkPcEventQueue();
void swapActiveThread();
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index cee6ada..ad58847 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -472,7 +472,7 @@
auto ®_file = regFiles[reg.classValue()];
const auto ®_class = reg_file.regClass;
- if (reg.index() == reg_class.zeroReg() || reg.is(InvalidRegClass))
+ if (reg.is(InvalidRegClass))
return;
DPRINTFV(reg_class.debug(), "Setting %s register %s (%d)
to %#x.\n",
@@ -488,7 +488,7 @@
auto ®_file = regFiles[reg.classValue()];
const auto ®_class = reg_file.regClass;
- if (reg.index() == reg_class.zeroReg() || reg.is(InvalidRegClass))
+ if (reg.is(InvalidRegClass))
return;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49746
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Gerrit-Change-Number: 49746
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
