[gem5-dev] Incorrect disassembly/register width in Aarch64 ?

[Arthur Perais via gem5-dev]

Hi all,

I am using a fairly old gem5 version 
(566c113de1eb08ccbfba6e4b074f96c9977a0e16 from Nov 2020), but I noticed 
that the disassembly (and the register width) of some Aarch64 
instructions seems to be incorrectly reported by gem5.

Notably, instruction :

ldr  w1, [sp, #168] (0xb940abe1 according to objdump)

Is reported in gem5 as

ldr  x1, [sp, #168] (0xf94057e1 according to objdump)

And the getIntWidth() method that can be called on the staticInst 
reports 64 (when it reports 32 for instructions that write into a "word" 
register).

I have not found a patch addressing this but maybe this has been fixed 
already, or maybe this is known to happen under some specific 
configuration of an Aarch64 system.

Best,

Arthur Perais
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