Hi Giacomo,
Thank you for the explanation, the base register is indeed SP here. I
will look into how your suggestion (intWidth per register) can be
implemented.
Arthur
On 12/1/21 11:58 AM, Giacomo Travaglini wrote:
Hi Arthur, this is a known issue in disassembling and arises when
multiple register operands have different width. For example your load
is likely using the 64-bit SP as base register and loading the value
into 32-bit w1.
Gem5 is not capturing this per-operand-width and it is reporting a
single intWidth of 64. A proper fix would involve having a per-operand
intWidth variable (or something similar)
Kind Regards
Giacomo
*From: *Arthur Perais via gem5-dev <gem5-dev@gem5.org>
*Date: *Tuesday, 30 November 2021 at 17:06
*To: *gem5-dev@gem5.org <gem5-dev@gem5.org>
*Cc: *Arthur Perais <arthur.per...@univ-grenoble-alpes.fr>
*Subject: *[gem5-dev] Incorrect disassembly/register width in Aarch64 ?
Hi all,
I am using a fairly old gem5 version
(566c113de1eb08ccbfba6e4b074f96c9977a0e16 from Nov 2020), but I noticed
that the disassembly (and the register width) of some Aarch64
instructions seems to be incorrectly reported by gem5.
Notably, instruction :
ldr w1, [sp, #168] (0xb940abe1 according to objdump)
Is reported in gem5 as
ldr x1, [sp, #168] (0xf94057e1 according to objdump)
And the getIntWidth() method that can be called on the staticInst
reports 64 (when it reports 32 for instructions that write into a "word"
register).
I have not found a patch addressing this but maybe this has been fixed
already, or maybe this is known to happen under some specific
configuration of an Aarch64 system.
Best,
Arthur Perais
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