Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55612 )
Change subject: dev-arm: Gicv3 implementation of the BaseGicRegisters
interface
......................................................................
dev-arm: Gicv3 implementation of the BaseGicRegisters interface
Signed-off-by: Giacomo Travaglini <[email protected]>
Change-Id: Iba23604cc6f7d5a1de91c287b4546154fcb20535
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
M src/dev/arm/base_gic.hh
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
12 files changed, 261 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 058ee6b..abc92e5 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -137,6 +137,12 @@
}
uint32_t
+KvmKernelGic::readRedistributor(ContextID ctx, Addr daddr)
+{
+ panic("%s not supported by KvmKernelGic\n", __func__);
+}
+
+uint32_t
KvmKernelGic::readCpu(ContextID ctx, Addr daddr)
{
auto vcpu = vm.contextIdToVCpuId(ctx);
@@ -151,6 +157,12 @@
}
void
+KvmKernelGic::writeRedistributor(ContextID ctx, Addr daddr, uint32_t data)
+{
+ panic("%s not supported by KvmKernelGic\n", __func__);
+}
+
+void
KvmKernelGic::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
{
auto vcpu = vm.contextIdToVCpuId(ctx);
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 3c021a1..49edc8e 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -115,10 +115,13 @@
/** BaseGicRegisters interface */
uint32_t readDistributor(ContextID ctx, Addr daddr) override;
+ uint32_t readRedistributor(ContextID ctx, Addr daddr) override;
uint32_t readCpu(ContextID ctx, Addr daddr) override;
void writeDistributor(ContextID ctx, Addr daddr,
uint32_t data) override;
+ void writeRedistributor(ContextID ctx, Addr daddr,
+ uint32_t data) override;
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
/* @} */
@@ -176,6 +179,20 @@
KvmKernelGicV2(KvmVM &vm,
const MuxingKvmGicV2Params ¶ms);
+ /** BaseGicRegisters interface */
+ RegVal
+ readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg) override
+ {
+ panic("%s not supported by KvmKernelGicV2\n", __func__);
+ }
+
+ void
+ writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg,
+ RegVal data) override
+ {
+ panic("%s not supported by KvmKernelGicV2\n", __func__);
+ }
+
private:
/** Address range for the CPU interfaces */
const AddrRange cpuRange;
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index 63b8679..277b380 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -46,6 +46,7 @@
#include <unordered_map>
#include <vector>
+#include "arch/arm/regs/misc.hh"
#include "arch/arm/system.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
@@ -73,11 +74,17 @@
{
public:
virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
+ virtual uint32_t readRedistributor(ContextID ctx, Addr daddr) = 0;
virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
+ virtual RegVal readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg) =
0;
virtual void writeDistributor(ContextID ctx, Addr daddr,
uint32_t data) = 0;
+ virtual void writeRedistributor(ContextID ctx, Addr daddr,
+ uint32_t data) = 0;
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
+ virtual void writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg,
+ RegVal data) = 0;
};
class BaseGic : public PioDevice
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 84694b6..21e34a5 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -526,12 +526,22 @@
{
return readDistributor(ctx, daddr, 4);
}
+ uint32_t
+ readRedistributor(ContextID ctx, Addr daddr) override
+ {
+ panic("%s not supported by GicV2\n", __func__);
+ }
/** Handle a read to the cpu portion of the GIC
* @param pkt packet to respond to
*/
Tick readCpu(PacketPtr pkt);
uint32_t readCpu(ContextID ctx, Addr daddr) override;
+ RegVal
+ readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg) override
+ {
+ panic("%s not supported by GicV2\n", __func__);
+ }
/** Handle a write to the distributor portion of the GIC
* @param pkt packet to respond to
@@ -544,12 +554,22 @@
{
return writeDistributor(ctx, daddr, data, 4);
}
+ void
+ writeRedistributor(ContextID ctx, Addr daddr, uint32_t data) override
+ {
+ panic("%s not supported by GicV2\n", __func__);
+ }
/** Handle a write to the cpu portion of the GIC
* @param pkt packet to respond to
*/
Tick writeCpu(PacketPtr pkt);
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
+ void
+ writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg, RegVal data)
override
+ {
+ panic("%s not supported by GicV2\n", __func__);
+ }
};
} // namespace gem5
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 223e86a..52459c2 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 ARM Limited
+ * Copyright (c) 2019-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -269,6 +269,87 @@
}
void
+Gicv3::copyRedistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr)
+{
+ auto val = from->readRedistributor(ctx, daddr);
+ DPRINTF(GIC, "copy redist 0x%x 0x%08x\n", daddr, val);
+ to->writeRedistributor(ctx, daddr, val);
+}
+
+void
+Gicv3::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, ArmISA::MiscRegIndex misc_reg)
+{
+ auto val = from->readCpu(ctx, misc_reg);
+ DPRINTF(GIC, "copy cpu %s 0x%08x\n", ArmISA::miscRegName[misc_reg],
val);
+ to->writeCpu(ctx, misc_reg, val);
+}
+
+void
+Gicv3::clearRedistRegister(BaseGicRegisters* to,
+ ContextID ctx, Addr daddr)
+{
+ to->writeRedistributor(ctx, daddr, 0xFFFFFFFF);
+}
+
+void
+Gicv3::copyRedistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr, size_t size)
+{
+ for (auto a = daddr; a < daddr + size; a += 4)
+ copyRedistRegister(from, to, ctx, a);
+}
+
+uint32_t
+Gicv3::readDistributor(ContextID ctx, Addr daddr)
+{
+ return distributor->read(daddr, 4, false);
+}
+
+uint32_t
+Gicv3::readRedistributor(ContextID ctx, Addr daddr)
+{
+ return redistributors[ctx]->read(daddr, 4, false);
+}
+
+RegVal
+Gicv3::readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg)
+{
+ return cpuInterfaces[ctx]->readMiscReg(misc_reg);
+}
+
+void
+Gicv3::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
+{
+ distributor->write(daddr, data, sizeof(data), false);
+}
+
+void
+Gicv3::writeRedistributor(ContextID ctx, Addr daddr, uint32_t data)
+{
+ redistributors[ctx]->write(daddr, data, sizeof(data), false);
+}
+
+void
+Gicv3::writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg, RegVal data)
+{
+ cpuInterfaces[ctx]->setMiscReg(misc_reg, data);
+}
+
+void
+Gicv3::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
+{
+ distributor->copy(from, to);
+ for (auto& redistributor : redistributors) {
+ redistributor->copy(from, to);
+ }
+ for (auto& cpu_interface : cpuInterfaces) {
+ cpu_interface->copy(from, to);
+ }
+}
+
+void
Gicv3::serialize(CheckpointOut & cp) const
{
distributor->serializeSection(cp, "distributor");
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 963beff..ef06b1e 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@
class Gicv3Redistributor;
class Gicv3Its;
-class Gicv3 : public BaseGic
+class Gicv3 : public BaseGic, public BaseGicRegisters
{
protected:
friend class Gicv3CPUInterface;
@@ -128,14 +128,7 @@
Tick write(PacketPtr pkt) override;
bool supportsVersion(GicVersion version) override;
- void
- copyGicState(BaseGicRegisters* from, BaseGicRegisters* to) override
- {
- panic("copyGicState unimplemented for Gicv3\n");
- }
-
public:
-
Gicv3(const Params &p);
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
void deassertAll(uint32_t cpu);
@@ -169,6 +162,38 @@
getRedistributorByAddr(Addr address) const;
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
+
+ protected: // GIC state transfer
+ void copyRedistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr);
+ void copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, ArmISA::MiscRegIndex misc_reg);
+ void clearRedistRegister(BaseGicRegisters* to,
+ ContextID ctx, Addr daddr);
+ void copyRedistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr, size_t size);
+
+ public: // BaseGicRegisters
+ void copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
override;
+
+ uint32_t readDistributor(ContextID ctx, Addr daddr) override;
+ uint32_t readRedistributor(ContextID ctx, Addr daddr) override;
+ RegVal readCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg) override;
+ uint32_t
+ readCpu(ContextID ctx, Addr daddr) override
+ {
+ panic("%s not supported by Gicv3\n", __func__);
+ }
+
+ void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
override;
+ void writeRedistributor(ContextID ctx, Addr daddr, uint32_t data)
override;
+ void writeCpu(ContextID ctx, ArmISA::MiscRegIndex misc_reg,
+ RegVal data) override;
+ void
+ writeCpu(ContextID ctx, Addr daddr, uint32_t data) override
+ {
+ panic("%s not supported by Gicv3\n", __func__);
+ }
};
} // namespace gem5
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 393adde..14b6e44 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2593,6 +2593,28 @@
}
void
+Gicv3CPUInterface::copy(BaseGicRegisters *from, BaseGicRegisters *to)
+{
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_PMR_EL1);
+
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_AP1R0_EL1);
+ if (PRIORITY_BITS >= 6) {
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_AP1R1_EL1);
+ }
+
+ if (PRIORITY_BITS >= 7) {
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_AP1R2_EL1);
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_AP1R3_EL1);
+ }
+
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_BPR1_EL1);
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_CTLR_EL1);
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_SRE_EL1);
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_IGRPEN0_EL1);
+ gic->copyCpuRegister(from, to, cpuId, MISCREG_ICC_IGRPEN1_EL1);
+}
+
+void
Gicv3CPUInterface::serialize(CheckpointOut & cp) const
{
SERIALIZE_SCALAR(hppi.intid);
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index eb16602..47a44fa 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -360,6 +360,9 @@
void init();
+ public:
+ void copy(BaseGicRegisters *from, BaseGicRegisters *to);
+
public: // BaseISADevice
RegVal readMiscReg(int misc_reg) override;
void setMiscReg(int misc_reg, RegVal val) override;
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index aff6b94..e98ceda 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -1182,6 +1182,29 @@
}
void
+Gicv3Distributor::copy(BaseGicRegisters *from, BaseGicRegisters *to)
+{
+ const size_t size = itLines / 8;
+
+ gic->copyDistRegister(from, to, 0, GICD_CTLR);
+
+ gic->clearDistRange(to, GICD_ICENABLER.start(), size);
+ gic->clearDistRange(to, GICD_ICPENDR.start(), size);
+ gic->clearDistRange(to, GICD_ICACTIVER.start(), size);
+
+ gic->copyDistRange(from, to, GICD_IGROUPR.start(), size);
+ gic->copyDistRange(from, to, GICD_ISENABLER.start(), size);
+ gic->copyDistRange(from, to, GICD_ISPENDR.start(), size);
+ gic->copyDistRange(from, to, GICD_ISACTIVER.start(), size);
+ gic->copyDistRange(from, to, GICD_IPRIORITYR.start(), size);
+ gic->copyDistRange(from, to, GICD_ITARGETSR.start(), size);
+ gic->copyDistRange(from, to, GICD_ICFGR.start(), size);
+ gic->copyDistRange(from, to, GICD_IGRPMODR.start(), size);
+ gic->copyDistRange(from, to, GICD_NSACR.start(), size);
+ gic->copyDistRange(from, to, GICD_IROUTER.start(), size);
+}
+
+void
Gicv3Distributor::serialize(CheckpointOut & cp) const
{
SERIALIZE_SCALAR(ARE);
diff --git a/src/dev/arm/gic_v3_distributor.hh
b/src/dev/arm/gic_v3_distributor.hh
index 22c5ad7..fa89a77 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -272,6 +272,8 @@
uint64_t read(Addr addr, size_t size, bool is_secure_access);
void write(Addr addr, uint64_t data, size_t size,
bool is_secure_access);
+
+ void copy(BaseGicRegisters *from, BaseGicRegisters *to);
};
} // namespace gem5
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index 0d8c7ff..a891b6c 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -1057,6 +1057,33 @@
}
void
+Gicv3Redistributor::copy(BaseGicRegisters *from, BaseGicRegisters *to)
+{
+ // SGI_Base regs
+ gic->copyRedistRegister(from, to, cpuId, GICR_CTLR);
+ gic->copyRedistRegister(from, to, cpuId, GICR_WAKER);
+
+ gic->clearRedistRegister(to, cpuId, GICR_ICENABLER0);
+ gic->clearRedistRegister(to, cpuId, GICR_ICPENDR0);
+ gic->clearRedistRegister(to, cpuId, GICR_ICACTIVER0);
+
+ gic->copyRedistRegister(from, to, cpuId, GICR_ISENABLER0);
+ gic->copyRedistRegister(from, to, cpuId, GICR_ISPENDR0);
+ gic->copyRedistRegister(from, to, cpuId, GICR_ISACTIVER0);
+ gic->copyRedistRegister(from, to, cpuId, GICR_ICFGR0);
+ gic->copyRedistRegister(from, to, cpuId, GICR_ICFGR1);
+ gic->copyRedistRegister(from, to, cpuId, GICR_IGRPMODR0);
+ gic->copyRedistRegister(from, to, cpuId, GICR_NSACR);
+
+ gic->copyRedistRange(from, to, cpuId,
+ GICR_IPRIORITYR.start(), GICR_IPRIORITYR.size());
+
+ // RD_Base regs
+ gic->copyRedistRegister(from, to, cpuId, GICR_PROPBASER);
+ gic->copyRedistRegister(from, to, cpuId, GICR_PENDBASER);
+}
+
+void
Gicv3Redistributor::serialize(CheckpointOut & cp) const
{
SERIALIZE_SCALAR(peInLowPowerState);
diff --git a/src/dev/arm/gic_v3_redistributor.hh
b/src/dev/arm/gic_v3_redistributor.hh
index 4d4bc99..d7778b5 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -260,6 +260,8 @@
void sendPPInt(uint32_t int_id);
void clearPPInt(uint32_t int_id);
void write(Addr addr, uint64_t data, size_t size, bool
is_secure_access);
+
+ void copy(BaseGicRegisters *from, BaseGicRegisters *to);
};
} // namespace gem5
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba23604cc6f7d5a1de91c287b4546154fcb20535
Gerrit-Change-Number: 55612
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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