Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/49701 )

 (

50 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one. )Change subject: arm: Replace readVecPredReg with getReg in the tarmac tracer.
......................................................................

arm: Replace readVecPredReg with getReg in the tarmac tracer.

Change-Id: Id290b4b63ca0cf9982327e1451d12917e9d99272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49701
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_record_v8.cc
2 files changed, 17 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index e8909a0..7abe1c2 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -786,8 +786,8 @@
             break;
           case REG_P:
             {
-                const ArmISA::VecPredRegContainer& pc =
- thread->readVecPredReg(RegId(VecPredRegClass, it->index));
+                ArmISA::VecPredRegContainer pc;
+                thread->getReg(RegId(VecPredRegClass, it->index), &pc);
                 auto pv = pc.as<uint8_t>();
                 uint64_t p = 0;
                 for (int i = maxVectorLength * 8; i > 0; ) {
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index 8dd96d1..f34a183 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -163,8 +163,8 @@
 )
 {
     auto thread = tarmCtx.thread;
-    const auto& pred_container = thread->readVecPredReg(
-        RegId(regClass, regRelIdx));
+    ArmISA::VecPredRegContainer pred_container;
+    thread->getReg(RegId(regClass, regRelIdx), &pred_container);

     // Predicate registers are always 1/8 the size of related vector
     // registers. (getCurSveVecLenInBits(thread) / 8)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49701
To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id290b4b63ca0cf9982327e1451d12917e9d99272
Gerrit-Change-Number: 49701
Gerrit-PatchSet: 52
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

Reply via email to