Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57191 )
Change subject: arch-x86: Add bsr and sret microops.
......................................................................
arch-x86: Add bsr and sret microops.
These were very briefly described in the original patent gem5's
microcode ISA is based on, but were never implemented.
Here, I'm assuming that calls can be exactly one level deep, and that
there is a special purpose register for holding the return microcode IP.
The encoding format for the sequence operator field in the patent does
not show space for a way to select where to store the return address,
and as far as I can see, there is no internal buffer which would let you
hold more than one value.
If deeper calls become necessary, and are deemed realistic, then we
could change the mechanism to keep a sort of register based stack for
return addresses. This would be significantly more complicated though,
since it would add a level of indirection when dealing with these
registers.
Change-Id: I20ad14e636015c15093f61fed0705ff6db13076b
---
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/operands.isa
M src/arch/x86/regs/int.hh
M src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
4 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/isa/microops/seqop.isa
b/src/arch/x86/isa/microops/seqop.isa
index 3720a3e..1761142 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -33,7 +33,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-def template BrDeclare {{
+def template BxrDeclare {{
class %(class_name)s : public %(base_class)s
{
private:
@@ -68,7 +68,7 @@
};
}};
-def template EretDeclare {{
+def template XretDeclare {{
class %(class_name)s : public %(base_class)s
{
private:
@@ -117,11 +117,34 @@
'cond_test': cond},
flags)
exec_output += SeqOpExecute.subst(iop)
- header_output += BrDeclare.subst(iop)
+ header_output += BxrDeclare.subst(iop)
+
+ iop = InstObjParams('bsr', 'Bsr' + suffix,
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase,
X86ISA::UpcOp>',
+ {'code': '''
+ RetUIP = nuIP;
+ nuIP = target;
+ ''',
+ 'else_code':
+ '''
+ RetUIP = RetUIP;
+ nuIP = nuIP;
+ ''',
+ 'cond_test': cond},
+ flags)
+ exec_output += SeqOpExecute.subst(iop)
+ header_output += BxrDeclare.subst(iop)
iop = InstObjParams('eret', 'Eret' + suffix,
'X86ISA::InstOperands<X86ISA::MicroCondBase>',
{'code': '', 'else_code': '', 'cond_test': cond}, flags)
exec_output += SeqOpExecute.subst(iop)
- header_output += EretDeclare.subst(iop)
+ header_output += XretDeclare.subst(iop)
+ iop = InstObjParams('sret', 'Sret' + suffix,
+ 'X86ISA::InstOperands<X86ISA::MicroCondBase>',
+ {'code': 'nuIP = RetUIP;', 'else_code': 'nuIP=nuIP;',
+ 'cond_test': cond},
+ flags)
+ exec_output += SeqOpExecute.subst(iop)
+ header_output += XretDeclare.subst(iop)
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 271c68a..147f524 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -111,6 +111,7 @@
'Remainder': intReg('X86ISA::INTREG_REMAINDER', 10),
'Divisor': intReg('X86ISA::INTREG_DIVISOR', 11),
'DoubleBits': intReg('X86ISA::INTREG_DOUBLEBITS', 11),
+ 'RetUIP': intReg('X86ISA::INTREG_RETURNUIP', 11),
'Rax': intReg('X86ISA::INTREG_RAX', 12),
'Rbx': intReg('X86ISA::INTREG_RBX', 13),
'Rcx': intReg('X86ISA::INTREG_RCX', 14),
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 014f5a4..3318aa1 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -164,6 +164,8 @@
INTREG_DIVISOR,
// The register to use for shift doubles.
INTREG_DOUBLEBITS,
+ // A return address for microcode "calls".
+ INTREG_RETURNUIP,
NUM_INTREGS,
};
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
index 010e602b..8ec1bee 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/seqop.py
@@ -65,6 +65,15 @@
microops['br'] = Br
+class Bsr(Br):
+ def __init__(self, target, flags=None):
+ super().__init__(target, flags)
+ self.className = 'Bsr'
+ if flags:
+ self.className += 'Flags'
+
+microops['bsr'] = Bsr
+
class Eret(X86Microop):
def __init__(self, flags=None):
super().__init__()
@@ -87,3 +96,21 @@
{self.microFlagsText(microFlags)}, {self.cond})'''
microops['eret'] = Eret
+
+class Sret(Eret):
+ def __init__(self, flags=None):
+ super().__init__(flags)
+ self.className = 'Sret'
+ if flags:
+ self.className += 'Flags'
+
+ def getAllocator(self, microFlags):
+ if 'IsLastMicroop' in microFlags:
+ microFlags.remove('IsLastMicroop')
+ if not 'IsDelayedCommit' in microFlags:
+ microFlags.append('IsDelayedCommit')
+
+ return f'''new {self.className}(machInst, macrocodeBlock,
+ {self.microFlagsText(microFlags)}, {self.cond})'''
+
+microops['sret'] = Sret
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20ad14e636015c15093f61fed0705ff6db13076b
Gerrit-Change-Number: 57191
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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