Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57192 )
Change subject: arch-x86: Extract gate type checks from the legacy int
macro.
......................................................................
arch-x86: Extract gate type checks from the legacy int macro.
Change-Id: Iaf86bfaa67ee4e5a22df57a035a01effe0aa84f0
---
M src/arch/x86/microcode/romutil.ucode
1 file changed, 68 insertions(+), 40 deletions(-)
diff --git a/src/arch/x86/microcode/romutil.ucode
b/src/arch/x86/microcode/romutil.ucode
index ea3241b..ab5f77e 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -176,29 +176,17 @@
undef macro long_int;
-def macro legacy_int start_label, gate_check_type="IntGateCheck",
with_ec=False
+def macro legacy_int label_prefix=rnd_str(), with_ec=False
{
- # This vectors the CPU into an interrupt handler in legacy mode.
- # On entry, t1 is set to the vector of the interrupt and t7 is the
current
- # ip. We need that because rdip returns the next ip.
- extern {start_label}:
-
- #
- # Get the interrupt, trap, or task gate descriptor from the IDT
- #
-
- # Load the gate descriptor from the IDT
- slli t4, t1, 3, dataSize=8
- ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
-
- # Make sure the descriptor is a legal gate.
- chks t0, t1, t4, {gate_check_type}, dataSize=8
+ # t1 = gate descriptor
+ # t7 = return IP
+ # t15 = error code (if any)
# Stick the target offset in t9.
- wrdh t9, t4, t0, dataSize=8
+ wrdh t9, t1, t0, dataSize=8
# Check the gate type.
- srli t2, t4, 40, dataSize=8
+ srli t2, t1, 40, dataSize=8
andi t2, t2, 0xf, dataSize=8
xori t2, t2, 0x5, flags=(EZF,), dataSize=8
@@ -209,7 +197,7 @@
# Get the target CS descriptor using the selector in the gate
# descriptor.
#
- srli t10, t4, 16, dataSize=8
+ srli t10, t1, 16, dataSize=8
m_read_descriptor desc="t3", selector="t10"
andi t13, t10, 0xff, dataSize=8
chks t13, t13, t3, IntCSCheck, dataSize=8
@@ -220,9 +208,9 @@
#
# Determine the operand size. ECF will be 1 if 32 bit, and 0 if 16 bit.
- srli t0, t4, 44, flags=(ECF,), dataSize=8
+ srli t0, t1, 44, flags=(ECF,), dataSize=8
- rdsel t1, cs, dataSize=8
+ rdsel t11, cs, dataSize=8
# Check if we're changing privelege level. At this point we can assume
# we're going to a DPL that's less than or equal to the CPL.
@@ -235,55 +223,55 @@
wrsel cs, t13, dataSize=8
wrdl cs, t3, t13, dataSize=8
- br "{start_label}_stackSwitch", flags=(nCEZF,)
+ br "{label_prefix}_stackSwitch", flags=(nCEZF,)
# Set up a temporary stack pointer.
mov t6, rsp, rsp, dataSize=8
m_copy_seg_info dest="hs", source="ss", temp_reg="t10"
- br "{start_label}_dszIs4", flags=(CECF,)
- br "{start_label}_dszIs2"
+ br "{label_prefix}_dszIs4", flags=(CECF,)
+ br "{label_prefix}_dszIs2"
-{start_label}_stackSwitch:
- br "{start_label}_switchDszIs4", flags=(CECF,)
+{label_prefix}_stackSwitch:
+ br "{label_prefix}_switchDszIs4", flags=(CECF,)
m_switch_legacy_stack new_ptr="t6", new_seg="hs", new_cpl="t5", \
temp_reg="t8", data_size=2
-{start_label}_dszIs2:
+{label_prefix}_dszIs2:
rflags t10, dataSize=8
st t10, hs, [1, t0, t6], -2, dataSize=2, addressSize=ssz
- st t1, hs, [1, t0, t6], -4, dataSize=2, addressSize=ssz
+ st t11, hs, [1, t0, t6], -4, dataSize=2, addressSize=ssz
st t7, hs, [1, t0, t6], -6, dataSize=2, addressSize=ssz
subi t6, t6, {8 if with_ec else 6}, dataSize=ssz
{"st t15, hs, [1, t0, t6], " if with_ec else "#"} \
{"dataSize=2, addressSize=ssz" if with_ec else ""}
- br "{start_label}_updateESP", flags=(CEZF,)
- br "{start_label}_updateSS"
+ br "{label_prefix}_updateESP", flags=(CEZF,)
+ br "{label_prefix}_updateSS"
-{start_label}_switchDszIs4:
+{label_prefix}_switchDszIs4:
m_switch_legacy_stack new_ptr="t6", new_seg="hs", new_cpl="t5", \
temp_reg="t8", data_size=4
-{start_label}_dszIs4:
+{label_prefix}_dszIs4:
rflags t10, dataSize=8
st t10, hs, [1, t0, t6], -4, dataSize=4, addressSize=ssz
- st t1, hs, [1, t0, t6], -8, dataSize=4, addressSize=ssz
+ st t11, hs, [1, t0, t6], -8, dataSize=4, addressSize=ssz
st t7, hs, [1, t0, t6], -12, dataSize=4, addressSize=ssz
subi t6, t6, {16 if with_ec else 12}, dataSize=ssz
{"st t15, ss, [1, t0, t6], " if with_ec else "#"} \
{"dataSize=4, addressSize=ssz" if with_ec else ""}
- br "{start_label}_updateESP", flags=(CEZF,)
+ br "{label_prefix}_updateESP", flags=(CEZF,)
-{start_label}_updateSS:
+{label_prefix}_updateSS:
m_copy_seg_info dest="ss", source="hs", temp_reg="t10"
-{start_label}_updateESP:
+{label_prefix}_updateESP:
mov rsp, rsp, t6, dataSize=4
wrip t0, t9, dataSize=8
@@ -294,7 +282,7 @@
# Set the TF, NT, RF, and VM bits. We'll flip them at the end.
limm t6, "(TFBit | NTBit | RFBit | VMBit)", dataSize=8
or t10, t10, t6, dataSize=8
- srli t5, t4, 40, dataSize=8
+ srli t5, t1, 40, dataSize=8
srli t7, t10, 9, dataSize=8
xor t5, t7, t5, dataSize=8
andi t5, t5, 1, dataSize=8
@@ -309,9 +297,40 @@
def rom
{
- legacy_int "legacyModeInterrupt"
- legacy_int "legacyModeSoftInterrupt",
gate_check_type="SoftIntGateCheck"
- legacy_int "legacyModeInterruptWithError", with_ec=True
+ # These vectors the CPU into an interrupt handler in legacy mode.
+ # On entry, t1 is set to the vector of the interrupt and t7 is the
current
+ # ip. We need that because rdip returns the next ip. t15 is the error
code,
+ # if any.
+
+legacy_mode_int_get_gate:
+ # Load the gate descriptor from the IDT
+ slli t1, t1, 3, dataSize=8
+ ld t1, idtr, [1, t0, t1], dataSize=8, addressSize=8, atCPL0=True
+
+ sret
+
+legacy_mode_int_finalize:
+
+extern legacyModeInterrupt:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, IntGateCheck, dataSize=8
+ legacy_int
+
+extern legacyModeSoftInterrupt:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, SoftIntGateCheck, dataSize=8
+ legacy_int
+
+extern legacyModeInterruptWithError:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, IntGateCheck, dataSize=8
+ legacy_int with_ec=True
};
undef macro legacy_int;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaf86bfaa67ee4e5a22df57a035a01effe0aa84f0
Gerrit-Change-Number: 57192
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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