Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65171?usp=email )
Change subject: arch-arm: Fix access permissions for GICv3 cpu registers
......................................................................
arch-arm: Fix access permissions for GICv3 cpu registers
* ICC_SRE_EL3/ICC_CTLR_EL3/MISCREG_ICC_IGRPEN1_EL3 are accessible at EL3
only
* ICH_LR<n>_EL2 are accessible at EL2 and EL3 only
Change-Id: Idcd9656abafc3014d2715cd6f138a6d786bc6c34
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/regs/misc.cc
1 file changed, 40 insertions(+), 35 deletions(-)
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index a534c65..349ebb2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -4612,32 +4612,38 @@
.hyp().mon()
.mapsTo(MISCREG_ICC_HSRE);
InitReg(MISCREG_ICC_CTLR_EL3)
- .allPrivileges().exceptUserMode()
+ .mon()
.mapsTo(MISCREG_ICC_MCTLR);
InitReg(MISCREG_ICC_SRE_EL3)
- .allPrivileges().exceptUserMode()
+ .mon()
.mapsTo(MISCREG_ICC_MSRE);
InitReg(MISCREG_ICC_IGRPEN1_EL3)
- .allPrivileges().exceptUserMode()
+ .mon()
.mapsTo(MISCREG_ICC_MGRPEN1);
InitReg(MISCREG_ICH_AP0R0_EL2)
.hyp().mon()
.mapsTo(MISCREG_ICH_AP0R0);
InitReg(MISCREG_ICH_AP0R1_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP0R1);
InitReg(MISCREG_ICH_AP0R2_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP0R2);
InitReg(MISCREG_ICH_AP0R3_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP0R3);
InitReg(MISCREG_ICH_AP1R0_EL2)
.hyp().mon()
.mapsTo(MISCREG_ICH_AP1R0);
InitReg(MISCREG_ICH_AP1R1_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP1R1);
InitReg(MISCREG_ICH_AP1R2_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP1R2);
InitReg(MISCREG_ICH_AP1R3_EL2)
+ .hyp().mon()
.mapsTo(MISCREG_ICH_AP1R3);
InitReg(MISCREG_ICH_HCR_EL2)
.hyp().mon()
@@ -4658,53 +4664,37 @@
.hyp().mon()
.mapsTo(MISCREG_ICH_VMCR);
InitReg(MISCREG_ICH_LR0_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR1_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR2_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR3_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR4_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR5_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR6_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR7_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR8_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR9_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR10_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR11_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR12_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR13_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR14_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
InitReg(MISCREG_ICH_LR15_EL2)
- .hyp().mon()
- .allPrivileges().exceptUserMode();
+ .hyp().mon();
// GICv3 AArch32
InitReg(MISCREG_ICC_AP0R0)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idcd9656abafc3014d2715cd6f138a6d786bc6c34
Gerrit-Change-Number: 65171
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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