Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70735?usp=email )
(
7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Fix too long lines in existing Arm NEON
instructons.
......................................................................
arch-arm: Fix too long lines in existing Arm NEON instructons.
These lines break the current gem5 coding guidelines.
Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70735
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon64.isa
2 files changed, 39 insertions(+), 26 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/formats/neon64.isa
b/src/arch/arm/isa/formats/neon64.isa
index c200da7..5cce0d7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2012-2013 ARM Limited
+// Copyright (c) 2012-2013, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1213,13 +1213,17 @@
switch (imm5_pos) {
case 0:
- return new InsElemX<uint8_t>(machInst, vd, vn, index1,
index2);
+ return new InsElemX<uint8_t>(
+ machInst, vd, vn, index1, index2);
case 1:
- return new InsElemX<uint16_t>(machInst, vd, vn, index1,
index2);
+ return new InsElemX<uint16_t>(
+ machInst, vd, vn, index1, index2);
case 2:
- return new InsElemX<uint32_t>(machInst, vd, vn, index1,
index2);
+ return new InsElemX<uint32_t>(
+ machInst, vd, vn, index1, index2);
case 3:
- return new InsElemX<uint64_t>(machInst, vd, vn, index1,
index2);
+ return new InsElemX<uint64_t>(
+ machInst, vd, vn, index1, index2);
default:
return new Unknown64(machInst);
}
@@ -1547,14 +1551,16 @@
if (u || (size == 0x0 || size == 0x3))
return new Unknown64(machInst);
else
- return decodeNeonSThreeImmHAndWReg<SqdmullElemX,
SqdmullElem2X>(
- q, size, machInst, vd, vn, vm, index);
+ return decodeNeonSThreeImmHAndWReg
+ <SqdmullElemX, SqdmullElem2X>(
+ q, size, machInst, vd, vn, vm, index);
case 0xc:
if (u || (size == 0x0 || size == 0x3))
return new Unknown64(machInst);
else
- return decodeNeonSThreeImmHAndWReg<SqdmulhElemDX,
SqdmulhElemQX>(
- q, size, machInst, vd, vn, vm, index);
+ return decodeNeonSThreeImmHAndWReg
+ <SqdmulhElemDX, SqdmulhElemQX>(
+ q, size, machInst, vd, vn, vm, index);
case 0xd:
if (u)
return decodeNeonSThreeImmHAndWReg<SqrdmlahElemDX,
@@ -2176,11 +2182,14 @@
switch (opcode) {
case 0x9:
- return decodeNeonSThreeHAndWReg<SqdmlalScX>(size, machInst,
vd, vn, vm);
+ return decodeNeonSThreeHAndWReg<SqdmlalScX>(
+ size, machInst, vd, vn, vm);
case 0xb:
- return decodeNeonSThreeHAndWReg<SqdmlslScX>(size, machInst,
vd, vn, vm);
+ return decodeNeonSThreeHAndWReg<SqdmlslScX>(
+ size, machInst, vd, vn, vm);
case 0xd:
- return decodeNeonSThreeHAndWReg<SqdmullScX>(size, machInst,
vd, vn, vm);
+ return decodeNeonSThreeHAndWReg<SqdmullScX>(
+ size, machInst, vd, vn, vm);
default:
return new Unknown64(machInst);
}
diff --git a/src/arch/arm/isa/insts/neon64.isa
b/src/arch/arm/isa/insts/neon64.isa
index e0083c9..0da7f06 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1,6 +1,6 @@
// -*- mode: c++ -*-
-// Copyright (c) 2012-2013, 2015-2018 ARM Limited
+// Copyright (c) 2012-2013, 2015-2018, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1993,9 +1993,9 @@
Element carryBit =
(((unsigned)srcElem1 & 0x1) +
((unsigned)srcElem2 & 0x1)) >> 1;
- // Use division instead of a shift to ensure the sign
extension works
- // right. The compiler will figure out if it can be a shift.
Mask the
- // inputs so they get truncated correctly.
+ // Use division instead of a shift to ensure the sign extension
+ // works right. The compiler will figure out if it can be a
shift.
+ // Mask the inputs so they get truncated correctly.
destElem = (((srcElem1 & ~(Element)1) / 2) +
((srcElem2 & ~(Element)1) / 2)) + carryBit;
'''
@@ -2035,9 +2035,9 @@
hsubCode = '''
Element borrowBit =
(((srcElem1 & 0x1) - (srcElem2 & 0x1)) >> 1) & 0x1;
- // Use division instead of a shift to ensure the sign
extension works
- // right. The compiler will figure out if it can be a shift.
Mask the
- // inputs so they get truncated correctly.
+ // Use division instead of a shift to ensure the sign extension
+ // works right. The compiler will figure out if it can be a
shift.
+ // Mask the inputs so they get truncated correctly.
destElem = (((srcElem1 & ~(Element)1) / 2) -
((srcElem2 & ~(Element)1) / 2)) - borrowBit;
'''
@@ -2802,7 +2802,8 @@
FPSCR fpscr = (FPSCR) FpscrQc;
destElem = srcElem1;
if (srcElem1 < 0 ||
- ((BigElement)destElem & mask(sizeof(Element) * 8)) !=
srcElem1) {
+ ((BigElement)destElem & mask(sizeof(Element) * 8))
+ != srcElem1) {
fpscr.qc = 1;
destElem = mask(sizeof(Element) * 8);
if (srcElem1 < 0)
@@ -2821,9 +2822,9 @@
Element carryBit =
(((unsigned)srcElem1 & 0x1) +
((unsigned)srcElem2 & 0x1) + 1) >> 1;
- // Use division instead of a shift to ensure the sign
extension works
- // right. The compiler will figure out if it can be a shift.
Mask the
- // inputs so they get truncated correctly.
+ // Use division instead of a shift to ensure the sign extension
+ // works right. The compiler will figure out if it can be a
shift.
+ // Mask the inputs so they get truncated correctly.
destElem = (((srcElem1 & ~(Element)1) / 2) +
((srcElem2 & ~(Element)1) / 2)) + carryBit;
'''
@@ -3013,7 +3014,8 @@
if (bits(destElem, sizeof(Element) * 8 - 1) == 0) {
if (bits(tmp, sizeof(Element) * 8 - 1) == 1 ||
tmp < srcElem1 || tmp < destElem) {
- destElem = (((Element) 1) << (sizeof(Element) * 8 -
1)) - 1;
+ destElem = (((Element) 1) << (sizeof(Element) * 8 - 1))
+ - 1;
fpscr.qc = 1;
} else {
destElem = tmp;
@@ -3021,9 +3023,11 @@
} else {
Element absDestElem = (~destElem) + 1;
if (absDestElem < srcElem1) {
- // Still check for positive sat., no need to check for
negative sat.
+ // Still check for positive sat., no need to check for
+ // negative sat.
if (bits(tmp, sizeof(Element) * 8 - 1) == 1) {
- destElem = (((Element) 1) << (sizeof(Element) * 8
- 1)) - 1;
+ destElem = (((Element) 1) << (sizeof(Element) * 8
- 1))
+ - 1;
fpscr.qc = 1;
} else {
destElem = tmp;
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f
Gerrit-Change-Number: 70735
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Richard Cooper <richard.coo...@arm.com>
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