changeset baeee670d4ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baeee670d4ce
description:
style: Make a style pass over the whole arch/alpha directory.
diffstat:
46 files changed, 776 insertions(+), 509 deletions(-)
src/arch/alpha/ev5.cc | 1
src/arch/alpha/ev5.hh | 2
src/arch/alpha/faults.cc | 1
src/arch/alpha/faults.hh | 5
src/arch/alpha/floatregfile.cc | 10 -
src/arch/alpha/floatregfile.hh | 13 +-
src/arch/alpha/freebsd/system.cc | 1
src/arch/alpha/idle_event.cc | 2
src/arch/alpha/intregfile.cc | 17 +--
src/arch/alpha/intregfile.hh | 25 +++-
src/arch/alpha/ipr.cc | 97 +++++++++++++++++-
src/arch/alpha/ipr.hh | 150 +++++++++++++++++++---------
src/arch/alpha/isa_traits.hh | 122 ----------------------
src/arch/alpha/linux/linux.cc | 2
src/arch/alpha/linux/linux.hh | 1
src/arch/alpha/linux/process.cc | 1
src/arch/alpha/linux/system.hh | 3
src/arch/alpha/locked_mem.hh | 1
src/arch/alpha/miscregfile.cc | 77 ++++++++++----
src/arch/alpha/miscregfile.hh | 49 +++++++--
src/arch/alpha/mmaped_ipr.hh | 1
src/arch/alpha/osfpal.cc | 3
src/arch/alpha/osfpal.hh | 1
src/arch/alpha/pagetable.cc | 20 +--
src/arch/alpha/pagetable.hh | 84 +++++++++++++++
src/arch/alpha/predecoder.hh | 35 ++++--
src/arch/alpha/process.cc | 1
src/arch/alpha/process.hh | 6 -
src/arch/alpha/regfile.cc | 35 +++---
src/arch/alpha/regfile.hh | 105 +++++++++----------
src/arch/alpha/remote_gdb.cc | 1
src/arch/alpha/remote_gdb.hh | 13 +-
src/arch/alpha/stacktrace.cc | 202 ++++++++++++++++++++++----------------
src/arch/alpha/stacktrace.hh | 59 ++++++++---
src/arch/alpha/syscallreturn.hh | 12 --
src/arch/alpha/system.hh | 3
src/arch/alpha/tlb.cc | 2
src/arch/alpha/tlb.hh | 1
src/arch/alpha/tru64/process.cc | 1
src/arch/alpha/tru64/process.hh | 4
src/arch/alpha/tru64/tru64.hh | 4
src/arch/alpha/types.hh | 29 ++++-
src/arch/alpha/utility.cc | 3
src/arch/alpha/utility.hh | 71 +++++++------
src/arch/alpha/vtophys.hh | 4
src/kern/tru64/tru64_events.cc | 5
diffs (truncated from 5133 to 300 lines):
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:48 2008 -0700
@@ -459,8 +459,7 @@
// really a control write
ipr[idx] = val;
- tc->getDTBPtr()->flushAddr(val,
- DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
+ tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
break;
case IPR_DTB_TAG: {
@@ -529,8 +528,7 @@
// really a control write
ipr[idx] = val;
- tc->getITBPtr()->flushAddr(val,
- ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
+ tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
break;
default:
@@ -541,18 +539,17 @@
// no error...
}
-
void
copyIprs(ThreadContext *src, ThreadContext *dest)
{
- for (int i = 0; i < NumInternalProcRegs; ++i) {
+ for (int i = 0; i < NumInternalProcRegs; ++i)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
- }
}
} // namespace AlphaISA
#if FULL_SYSTEM
+
using namespace AlphaISA;
Fault
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/ev5.hh Sat Sep 27 21:03:48 2008 -0700
@@ -65,7 +65,9 @@
const Addr PAddrUncachedBit40 = ULL(0x10000000000);
const Addr PAddrUncachedBit43 = ULL(0x80000000000);
const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
-inline Addr Phys2K0Seg(Addr addr)
+
+inline Addr
+Phys2K0Seg(Addr addr)
{
#if !ALPHA_TLASER
if (addr & PAddrUncachedBit43) {
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/faults.cc Sat Sep 27 21:03:48 2008 -0700
@@ -40,8 +40,7 @@
#include "mem/page_table.hh"
#endif
-namespace AlphaISA
-{
+namespace AlphaISA {
FaultName MachineCheckFault::_name = "mchk";
FaultVect MachineCheckFault::_vect = 0x0401;
@@ -109,7 +108,8 @@
#if FULL_SYSTEM
-void AlphaFault::invoke(ThreadContext * tc)
+void
+AlphaFault::invoke(ThreadContext *tc)
{
FaultBase::invoke(tc);
countStat()++;
@@ -128,29 +128,31 @@
tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
-void ArithmeticFault::invoke(ThreadContext * tc)
+void
+ArithmeticFault::invoke(ThreadContext *tc)
{
FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
-void DtbFault::invoke(ThreadContext * tc)
+void
+DtbFault::invoke(ThreadContext *tc)
{
// Set fault address and flags. Even though we're modeling an
// EV5, we use the EV6 technique of not latching fault registers
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
- if (!tc->misspeculating()
- && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
+ if (!tc->misspeculating() &&
+ !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
// set MM_STAT register flags
tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(tc->getInst()) & 0x3f) << 11)
- | ((Ra(tc->getInst()) & 0x1f) << 6)
- | (flags & 0x3f)));
+ (((Opcode(tc->getInst()) & 0x3f) << 11) |
+ ((Ra(tc->getInst()) & 0x1f) << 6) |
+ (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
tc->setMiscRegNoEffect(IPR_VA_FORM,
@@ -160,13 +162,13 @@
AlphaFault::invoke(tc);
}
-void ItbFault::invoke(ThreadContext * tc)
+void
+ItbFault::invoke(ThreadContext *tc)
{
if (!tc->misspeculating()) {
tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) |
- (VAddr(pc).vpn() << 3));
+ tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
}
AlphaFault::invoke(tc);
@@ -174,12 +176,13 @@
#else
-void ItbPageFault::invoke(ThreadContext * tc)
+void
+ItbPageFault::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(pc, entry);
- if(!success) {
+ if (!success) {
panic("Tried to execute unmapped address %#x.\n", pc);
} else {
VAddr vaddr(pc);
@@ -187,16 +190,17 @@
}
}
-void NDtbMissFault::invoke(ThreadContext * tc)
+void
+NDtbMissFault::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
- if(!success) {
+ if (!success) {
p->checkAndAllocNextPage(vaddr);
success = p->pTable->lookup(vaddr, entry);
}
- if(!success) {
+ if (!success) {
panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
} else {
tc->getDTBPtr()->insert(vaddr.page(), entry);
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/faults.hh
--- a/src/arch/alpha/faults.hh Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/faults.hh Sat Sep 27 21:03:48 2008 -0700
@@ -29,18 +29,16 @@
* Kevin Lim
*/
-#ifndef __ALPHA_FAULTS_HH__
-#define __ALPHA_FAULTS_HH__
+#ifndef __ARCH_ALPHA_FAULTS_HH__
+#define __ARCH_ALPHA_FAULTS_HH__
+#include "arch/alpha/pagetable.hh"
#include "config/full_system.hh"
#include "sim/faults.hh"
-#include "arch/alpha/pagetable.hh"
-
// The design of the "name" and "vect" functions is in sim/faults.hh
-namespace AlphaISA
-{
+namespace AlphaISA {
typedef const Addr FaultVect;
@@ -63,6 +61,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
@@ -76,6 +75,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
@@ -94,6 +94,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
@@ -102,12 +103,14 @@
class ArithmeticFault : public AlphaFault
{
- protected:
- bool skipFaultingInstruction() {return true;}
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
+ protected:
+ bool skipFaultingInstruction() {return true;}
+
public:
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
@@ -119,12 +122,14 @@
class InterruptFault : public AlphaFault
{
- protected:
- bool setRestartAddress() {return false;}
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
+ protected:
+ bool setRestartAddress() {return false;}
+
public:
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
@@ -137,6 +142,7 @@
VAddr vaddr;
uint32_t reqFlags;
uint64_t flags;
+
public:
DtbFault(VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
@@ -155,6 +161,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
NDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
@@ -173,6 +180,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
PDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
@@ -188,6 +196,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
DtbPageFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
@@ -203,6 +212,7 @@
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
+
public:
DtbAcvFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
@@ -218,6 +228,7 @@
static FaultName _name;
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