On Thu, 22 Oct 2009 09:36:49 +0100, Gabe Black <gbl...@eecs.umich.edu> wrote:
> Timothy M Jones wrote: >> On Wed, 21 Oct 2009 18:12:59 +0100, Gabe Black <gbl...@eecs.umich.edu> >> wrote: >> >> >>> In the simple CPU, the requests are all translated before any are sent, >>> so you can't have something half in the memory system and then take a >>> fault on it. I don't know exactly how that would map to O3. I believe >>> it's fine to do 3 bytes and 1 byte as two requests since they only have >>> to avoid block boundaries, not necessarily be aligned on size >>> boundaries. That's what x86 does. >>> >>> >> From what I've seen, O3 already does an atomic translation before >> sending >> the request, so I can just extend that to do two of them. In that way >> I'll >> also ensure that nothing is half-done. >> >> Cheers >> Tim >> >> > The translation is atomic since I didn't take the time to set it up as a > timing translation like it technically should be. If you'd be willing, > making it into a timing translation while you're allowing split accesses > would be helpful for x86 in the future. > No problem. I'll see what I can do. Cheers Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
