# HG changeset patch # User Brad Beckmann <brad.beckm...@amd.com> # Date 1260657436 28800 # Node ID e68f680829daff5e16ea6d520c7302f7ed5055f9 # Parent 3518bdc98c5697d49bc20c3955e2013977f1e6c8 ruby: Converted MOESI_hammer dma cntrl to new config system
diff -r 3518bdc98c56 -r e68f680829da configs/example/memtest-ruby.py --- a/configs/example/memtest-ruby.py Sat Dec 12 14:37:16 2009 -0800 +++ b/configs/example/memtest-ruby.py Sat Dec 12 14:37:16 2009 -0800 @@ -104,6 +104,7 @@ # l1_cntrl_nodes = [] dir_cntrl_nodes = [] +dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the @@ -138,12 +139,15 @@ directory = RubyDirectoryMemory(), memBuffer = RubyMemoryControl()) + dma_cntrl = DMA_Controller(version = i, + dma_sequencer = DMASequencer()) # # As noted above: Two independent list are track to maintain the order of # nodes/controllers assumed by the ruby network # l1_cntrl_nodes.append(l1_cntrl) dir_cntrl_nodes.append(dir_cntrl) + dma_cntrl_nodes.append(dma_cntrl) # # Finally tie the memtester ports to the correct system ports @@ -157,7 +161,8 @@ # constructor. # network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \ - dir_cntrl_nodes)) + dir_cntrl_nodes + \ + dma_cntrl_nodes)) mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \ for dir_cntrl in dir_cntrl_nodes]) @@ -166,7 +171,9 @@ network = network, profiler = RubyProfiler(), tracer = RubyTracer(), - debug = RubyDebug(), + debug = RubyDebug(filter_string = 'qQin', + verbosity_string = 'high', + protocol_trace = True), mem_size_mb = mem_size_mb) diff -r 3518bdc98c56 -r e68f680829da src/mem/protocol/MOESI_hammer-dma.sm --- a/src/mem/protocol/MOESI_hammer-dma.sm Sat Dec 12 14:37:16 2009 -0800 +++ b/src/mem/protocol/MOESI_hammer-dma.sm Sat Dec 12 14:37:16 2009 -0800 @@ -28,7 +28,8 @@ machine(DMA, "DMA Controller") -: int request_latency = 6 +: DMASequencer * dma_sequencer, + int request_latency = 6 { MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true"; @@ -47,20 +48,14 @@ Ack, desc="DMA write to memory completed"; } - external_type(DMASequencer) { - void ackCallback(); - void dataCallback(DataBlock); - } - MessageBuffer mandatoryQueue, ordered="false", no_vector="true"; - DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true"; State cur_state, no_vector="true"; State getState(Address addr) { return cur_state; } void setState(Address addr, State state) { - cur_state := state; + cur_state := state; } out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); diff -r 3518bdc98c56 -r e68f680829da src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Sat Dec 12 14:37:16 2009 -0800 +++ b/src/mem/protocol/RubySlicc_Types.sm Sat Dec 12 14:37:16 2009 -0800 @@ -122,6 +122,11 @@ } +external_type(DMASequencer) { + void ackCallback(); + void dataCallback(DataBlock); +} + external_type(TimerTable, inport="yes") { bool isReady(); Address readyAddress(); diff -r 3518bdc98c56 -r e68f680829da src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Sat Dec 12 14:37:16 2009 -0800 +++ b/src/mem/ruby/system/DMASequencer.cc Sat Dec 12 14:37:16 2009 -0800 @@ -8,6 +8,10 @@ #include "mem/protocol/SequencerRequestType.hh" #include "mem/ruby/system/System.hh" +// +// Fix me: This code needs comments! +// + DMASequencer::DMASequencer(const Params *p) : RubyPort(p) { @@ -58,11 +62,16 @@ msg.getLineAddress() = line_address(msg.getPhysicalAddress()); msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; int offset = paddr & m_data_block_mask; + msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? len : RubySystem::getBlockSizeBytes() - offset; - if (write) + + if (write) { msg.getDataBlk().setData(data, offset, msg.getLen()); + } + + assert(m_mandatory_q_ptr != NULL); m_mandatory_q_ptr->enqueue(msg); active_request.bytes_issued += msg.getLen(); @@ -82,14 +91,18 @@ SequencerMsg msg; msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed); + assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); msg.getLineAddress() = line_address(msg.getPhysicalAddress()); + msg.getType() = (active_request.write ? SequencerRequestType_ST : SequencerRequestType_LD); + msg.getLen() = (active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? active_request.len - active_request.bytes_completed : RubySystem::getBlockSizeBytes()); + if (active_request.write) { msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen()); @@ -97,6 +110,8 @@ } else { msg.getType() = SequencerRequestType_LD; } + + assert(m_mandatory_q_ptr != NULL); m_mandatory_q_ptr->enqueue(msg); active_request.bytes_issued += msg.getLen(); } diff -r 3518bdc98c56 -r e68f680829da src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py Sat Dec 12 14:37:16 2009 -0800 +++ b/src/mem/slicc/symbols/StateMachine.py Sat Dec 12 14:37:16 2009 -0800 @@ -38,6 +38,7 @@ "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", "MemoryControl": "RubyMemoryControl", + "DMASequencer": "DMASequencer" } class StateMachine(Symbol): _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev