# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1263536247 28800
# Node ID 061151fda49a35f2d8ba4a20d2ed159c9ed23493
# Parent 54967d761bd18605f9fdf1210e8898ae942c7c04
ruby: MOESI_CMP_token updates to use the new config system
diff -r 54967d761bd1 -r 061151fda49a configs/common/Options.py
--- a/configs/common/Options.py Thu Jan 14 22:17:27 2010 -0800
+++ b/configs/common/Options.py Thu Jan 14 22:17:27 2010 -0800
@@ -36,6 +36,7 @@
parser.add_option("--fastmem", action="store_true")
parser.add_option("--clock", action="store", type="string", default='1GHz')
parser.add_option("--num-dirs", type="int", default=1)
+parser.add_option("--num-l2caches", type="int", default=1)
# Run duration options
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
diff -r 54967d761bd1 -r 061151fda49a configs/ruby/MOESI_CMP_token.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/ruby/MOESI_CMP_token.py Thu Jan 14 22:17:27 2010 -0800
@@ -0,0 +1,161 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
+ panic("This script requires the MOESI_CMP_token protocol to be built.")
+
+ #
+ # number of tokens that the owner passes to requests so that shared blocks
can
+ # respond to read requests
+ #
+ n_tokens = options.num_cpus + 1
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes
must be
+ # listed before the directory nodes and directory nodes before dma nodes,
etc.
+ #
+ l1_cntrl_nodes = []
+ l2_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+ cpu_seq = RubySequencer(icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2),
+ N_tokens = n_tokens)
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ for i in xrange(options.num_l2caches):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
+
+ l2_cntrl = L2Cache_Controller(version = i,
+ L2cacheMemory = l2_cache,
+ N_tokens = n_tokens)
+
+ l2_cntrl_nodes.append(l2_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) +
1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size),
+ memBuffer = mem_cntrl,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2))
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + \
+ l2_cntrl_nodes + \
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff -r 54967d761bd1 -r 061151fda49a configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Thu Jan 14 22:17:27 2010 -0800
+++ b/configs/ruby/Ruby.py Thu Jan 14 22:17:27 2010 -0800
@@ -34,6 +34,7 @@
import MOESI_hammer
import MI_example
+import MOESI_CMP_token
def create_system(options, physmem, piobus = None, dma_devices = []):
@@ -51,6 +52,12 @@
physmem, \
piobus, \
dma_devices)
+ elif protocol == "MOESI_CMP_token":
+ (cpu_sequencers, dir_cntrls, all_cntrls) = \
+ MOESI_CMP_token.create_system(options, \
+ physmem, \
+ piobus, \
+ dma_devices)
else:
print "Error: unsupported ruby protocol"
sys.exit(1)
diff -r 54967d761bd1 -r 061151fda49a src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Thu Jan 14 22:17:27
2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Thu Jan 14 22:17:27
2010 -0800
@@ -33,14 +33,17 @@
*/
machine(L1Cache, "Token protocol")
- : int l1_request_latency,
- int l1_response_latency,
- int l2_select_low_bit,
+ : Sequencer * sequencer,
+ CacheMemory * L1IcacheMemory,
+ CacheMemory * L1DcacheMemory,
int l2_select_num_bits,
int N_tokens,
- int retry_threshold,
- int fixed_timeout_latency,
- bool dynamic_timeout_enabled
+ int l1_request_latency = 2,
+ int l1_response_latency = 2,
+ int l2_select_low_bit = 6,
+ int retry_threshold = 1,
+ int fixed_timeout_latency = 300,
+ bool dynamic_timeout_enabled = true
{
// From this node's L1 cache TO the network
@@ -147,16 +150,6 @@
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
- external_type(CacheMemory) {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- void allocate(Address, Entry);
- void deallocate(Address);
- Entry lookup(Address);
- void changePermission(Address, AccessPermission);
- bool isTagPresent(Address);
- }
-
external_type(TBETable) {
TBE lookup(Address);
void allocate(Address);
@@ -177,11 +170,8 @@
}
TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
- CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])';
- CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])';
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
- Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
bool starving, default="false";
@@ -218,17 +208,17 @@
Entry getCacheEntry(Address addr), return_by_ref="yes" {
if (L1DcacheMemory.isTagPresent(addr)) {
- return L1DcacheMemory[addr];
+ return static_cast(Entry, L1DcacheMemory[addr]);
} else {
- return L1IcacheMemory[addr];
+ return static_cast(Entry, L1IcacheMemory[addr]);
}
}
int getTokens(Address addr) {
if (L1DcacheMemory.isTagPresent(addr)) {
- return L1DcacheMemory[addr].Tokens;
+ return static_cast(Entry, L1DcacheMemory[addr]).Tokens;
} else if (L1IcacheMemory.isTagPresent(addr)) {
- return L1IcacheMemory[addr].Tokens;
+ return static_cast(Entry, L1IcacheMemory[addr]).Tokens;
} else {
return 0;
}
diff -r 54967d761bd1 -r 061151fda49a src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Thu Jan 14 22:17:27
2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Thu Jan 14 22:17:27
2010 -0800
@@ -33,10 +33,11 @@
*/
machine(L2Cache, "Token protocol")
- : int l2_request_latency,
- int l2_response_latency,
+ : CacheMemory * L2cacheMemory,
int N_tokens,
- bool filtering_enabled
+ int l2_request_latency = 10,
+ int l2_response_latency = 10,
+ bool filtering_enabled = true
{
// L2 BANK QUEUES
@@ -125,17 +126,6 @@
bool exclusive, default="false", desc="if local exclusive is likely";
}
- external_type(CacheMemory) {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- void allocate(Address, Entry);
- void deallocate(Address);
- Entry lookup(Address);
- void changePermission(Address, AccessPermission);
- bool isTagPresent(Address);
- void setMRU(Address);
- }
-
external_type(PerfectCacheMemory) {
void allocate(Address);
void deallocate(Address);
@@ -154,22 +144,20 @@
int countReadStarvingForAddress(Address);
}
- CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
-
PersistentTable persistentTable;
PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>";
Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
if (L2cacheMemory.isTagPresent(addr)) {
- return L2cacheMemory[addr];
+ return static_cast(Entry, L2cacheMemory[addr]);
}
assert(false);
- return L2cacheMemory[addr];
+ return static_cast(Entry, L2cacheMemory[addr]);
}
int getTokens(Address addr) {
if (L2cacheMemory.isTagPresent(addr)) {
- return L2cacheMemory[addr].Tokens;
+ return getL2CacheEntry(addr).Tokens;
} else {
return 0;
}
diff -r 54967d761bd1 -r 061151fda49a src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Thu Jan 14 22:17:27 2010 -0800
@@ -33,11 +33,13 @@
machine(Directory, "Token protocol")
- : int directory_latency,
- int l2_select_low_bit,
+ : DirectoryMemory * directory,
+ MemoryControl * memBuffer,
int l2_select_num_bits,
- bool distributed_persistent,
- int fixed_timeout_latency
+ int directory_latency = 6,
+ int l2_select_low_bit = 6,
+ bool distributed_persistent = true,
+ int fixed_timeout_latency = 300
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="0",
ordered="true";
@@ -104,7 +106,7 @@
// TYPES
// DirectoryEntry
- structure(Entry, desc="...") {
+ structure(Entry, desc="...", interface="AbstractEntry") {
State DirectoryState, desc="Directory state";
DataBlock DataBlk, desc="data for the block";
int Tokens, default="max_tokens()", desc="Number of tokens for the line
we're holding";
@@ -118,15 +120,6 @@
Set Sharers, desc="Probable sharers of the line. More
accurately, the set of processors who need to see a GetX";
}
- external_type(DirectoryMemory) {
- Entry lookup(Address);
- bool isPresent(Address);
- }
-
- external_type(MemoryControl, inport="yes", outport="yes") {
-
- }
-
external_type(PersistentTable) {
void persistentRequestLock(Address, MachineID, AccessType);
void persistentRequestUnlock(Address, MachineID);
@@ -159,10 +152,6 @@
// ** OBJECTS **
- DirectoryMemory directory,
factory='RubySystem::getDirectory(m_cfg["directory_name"])';
-
- MemoryControl memBuffer,
factory='RubySystem::getMemoryControl(m_cfg["memory_controller_name"])';
-
PersistentTable persistentTable;
TimerTable reissueTimerTable;
@@ -170,11 +159,15 @@
bool starving, default="false";
+ Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
+ return static_cast(Entry, directory[addr]);
+ }
+
State getState(Address addr) {
if (TBEs.isPresent(addr)) {
return TBEs[addr].TBEState;
} else {
- return directory[addr].DirectoryState;
+ return getDirectoryEntry(addr).DirectoryState;
}
}
@@ -182,22 +175,22 @@
if (TBEs.isPresent(addr)) {
TBEs[addr].TBEState := state;
}
- directory[addr].DirectoryState := state;
+ getDirectoryEntry(addr).DirectoryState := state;
if (state == State:L) {
- assert(directory[addr].Tokens == 0);
+ assert(getDirectoryEntry(addr).Tokens == 0);
}
// We have one or zero owners
- assert((directory[addr].Owner.count() == 0) ||
(directory[addr].Owner.count() == 1));
+ assert((getDirectoryEntry(addr).Owner.count() == 0) ||
(getDirectoryEntry(addr).Owner.count() == 1));
// Make sure the token count is in range
- assert(directory[addr].Tokens >= 0);
- assert(directory[addr].Tokens <= max_tokens());
+ assert(getDirectoryEntry(addr).Tokens >= 0);
+ assert(getDirectoryEntry(addr).Tokens <= max_tokens());
if (state == State:O) {
- assert(directory[addr].Tokens >= 1); // Must have at least one token
- // assert(directory[addr].Tokens >= (max_tokens() / 2)); // Only mostly
true; this might not always hold
+ assert(getDirectoryEntry(addr).Tokens >= 1); // Must have at least one
token
+ // assert(getDirectoryEntry(addr).Tokens >= (max_tokens() / 2)); // Only
mostly true; this might not always hold
}
}
@@ -249,7 +242,7 @@
if (responseNetwork_in.isReady()) {
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID));
- if (directory[in_msg.Address].Tokens + in_msg.Tokens == max_tokens()) {
+ if (getDirectoryEntry(in_msg.Address).Tokens + in_msg.Tokens ==
max_tokens()) {
if ((in_msg.Type == CoherenceResponseType:DATA_OWNER) ||
(in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
trigger(Event:Data_All_Tokens, in_msg.Address);
@@ -338,7 +331,7 @@
if (in_msg.Type == DMARequestType:READ) {
trigger(Event:DMA_READ, in_msg.LineAddress);
} else if (in_msg.Type == DMARequestType:WRITE) {
- if (directory[in_msg.LineAddress].Tokens == max_tokens()) {
+ if (getDirectoryEntry(in_msg.LineAddress).Tokens == max_tokens()) {
trigger(Event:DMA_WRITE_All_Tokens, in_msg.LineAddress);
} else {
trigger(Event:DMA_WRITE, in_msg.LineAddress);
@@ -354,7 +347,7 @@
action(a_sendTokens, "a", desc="Send tokens to requestor") {
// Only send a message if we have tokens to send
- if (directory[address].Tokens > 0) {
+ if (getDirectoryEntry(address).Tokens > 0) {
peek(requestNetwork_in, RequestMsg) {
// enqueue(responseNetwork_out, ResponseMsg,
latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency)
{// FIXME?
@@ -363,11 +356,11 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:Directory;
out_msg.Destination.add(in_msg.Requestor);
- out_msg.Tokens := directory[in_msg.Address].Tokens;
+ out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
- directory[address].Tokens := 0;
+ getDirectoryEntry(address).Tokens := 0;
}
}
@@ -419,7 +412,7 @@
//
// Assser that we only send message if we don't already have all the
tokens
//
- assert(directory[address].Tokens != max_tokens());
+ assert(getDirectoryEntry(address).Tokens != max_tokens());
enqueue(requestNetwork_out, RequestMsg, latency = "1") {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETX;
@@ -513,7 +506,7 @@
action(aa_sendTokensToStarver, "\a", desc="Send tokens to starver") {
// Only send a message if we have tokens to send
- if (directory[address].Tokens > 0) {
+ if (getDirectoryEntry(address).Tokens > 0) {
// enqueue(responseNetwork_out, ResponseMsg,
latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {//
FIXME?
out_msg.Address := address;
@@ -521,10 +514,10 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:Directory;
out_msg.Destination.add(persistentTable.findSmallest(address));
- out_msg.Tokens := directory[address].Tokens;
+ out_msg.Tokens := getDirectoryEntry(address).Tokens;
out_msg.MessageSize := MessageSizeType:Response_Control;
}
- directory[address].Tokens := 0;
+ getDirectoryEntry(address).Tokens := 0;
}
}
@@ -536,14 +529,14 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:Directory;
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
- assert(directory[address].Tokens > 0);
- out_msg.Tokens := directory[in_msg.Address].Tokens;
- out_msg.DataBlk := directory[in_msg.Address].DataBlk;
+ assert(getDirectoryEntry(address).Tokens > 0);
+ out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
+ out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
out_msg.Dirty := false;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
- directory[address].Tokens := 0;
+ getDirectoryEntry(address).Tokens := 0;
}
action(dd_sendDataWithAllTokensToStarver, "\d", desc="Send data and tokens
to starver") {
@@ -554,14 +547,14 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:Directory;
out_msg.Destination.add(persistentTable.findSmallest(address));
- assert(directory[address].Tokens > 0);
- out_msg.Tokens := directory[address].Tokens;
- out_msg.DataBlk := directory[address].DataBlk;
+ assert(getDirectoryEntry(address).Tokens > 0);
+ out_msg.Tokens := getDirectoryEntry(address).Tokens;
+ out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
out_msg.Dirty := false;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
- directory[address].Tokens := 0;
+ getDirectoryEntry(address).Tokens := 0;
}
action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch
request") {
@@ -572,7 +565,7 @@
out_msg.Sender := machineID;
out_msg.OriginalRequestorMachId := in_msg.Requestor;
out_msg.MessageSize := in_msg.MessageSize;
- out_msg.DataBlk := directory[address].DataBlk;
+ out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
DEBUG_EXPR(out_msg);
}
}
@@ -586,7 +579,7 @@
out_msg.Sender := machineID;
out_msg.OriginalRequestorMachId := in_msg.Requestor;
out_msg.MessageSize := in_msg.MessageSize;
- out_msg.DataBlk := directory[address].DataBlk;
+ out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
DEBUG_EXPR(out_msg);
}
}
@@ -673,18 +666,18 @@
}
action(cd_writeCleanDataToTbe, "cd", desc="Write clean memory data to TBE") {
- TBEs[address].DataBlk := directory[address].DataBlk;
+ TBEs[address].DataBlk := getDirectoryEntry(address).DataBlk;
}
action(dwt_writeDmaDataFromTBE, "dwt", desc="DMA Write data to memory from
TBE") {
- directory[address].DataBlk := TBEs[address].DataBlk;
- directory[address].DataBlk.copyPartial(TBEs[address].DmaDataBlk,
addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
+ getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
+ getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DmaDataBlk,
addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
}
action(f_incrementTokens, "f", desc="Increment the number of tokens we're
tracking") {
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Tokens >= 1);
- directory[address].Tokens := directory[address].Tokens + in_msg.Tokens;
+ getDirectoryEntry(address).Tokens := getDirectoryEntry(address).Tokens +
in_msg.Tokens;
}
}
@@ -722,7 +715,7 @@
action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
peek(responseNetwork_in, ResponseMsg) {
- directory[in_msg.Address].DataBlk := in_msg.DataBlk;
+ getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
DEBUG_EXPR(in_msg.Address);
DEBUG_EXPR(in_msg.DataBlk);
}
@@ -730,7 +723,7 @@
action(n_checkData, "n", desc="Check incoming clean data message") {
peek(responseNetwork_in, ResponseMsg) {
- assert(directory[in_msg.Address].DataBlk == in_msg.DataBlk);
+ assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
}
}
@@ -773,7 +766,7 @@
// implementation. We include the data in the "dataless"
// message so we can assert the clean data matches the datablock
// in memory
- assert(directory[in_msg.Address].DataBlk == in_msg.DataBlk);
+ assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
// Bounce the message, but "re-associate" the data and the owner
// token. In essence we're converting an ACK_OWNER message to a
@@ -786,7 +779,7 @@
out_msg.DestMachine := MachineType:L1Cache;
out_msg.Destination.add(persistentTable.findSmallest(address));
out_msg.Tokens := in_msg.Tokens;
- out_msg.DataBlk := directory[in_msg.Address].DataBlk;
+ out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
out_msg.Dirty := in_msg.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
diff -r 54967d761bd1 -r 061151fda49a src/mem/protocol/MOESI_CMP_token-dma.sm
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Thu Jan 14 22:17:27 2010 -0800
@@ -28,7 +28,8 @@
machine(DMA, "DMA Controller")
-: int request_latency
+: DMASequencer * dma_sequencer,
+ int request_latency
{
MessageBuffer responseFromDir, network="From", virtual_network="0",
ordered="true", no_vector="true";
@@ -53,7 +54,6 @@
}
MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- DMASequencer dma_sequencer,
factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
State cur_state, no_vector="true";
State getState(Address addr) {
diff -r 54967d761bd1 -r 061151fda49a src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:27 2010 -0800
@@ -117,6 +117,7 @@
void changePermission(Address, AccessPermission);
bool isTagPresent(Address);
void profileMiss(CacheMsg);
+ void setMRU(Address);
}
external_type(MemoryControl, inport="yes", outport="yes") {
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