[m5-dev] [PATCH 25 of 41] ruby: Added Cache and MemCntrl profiler calls

[Brad Beckmann]

# HG changeset patch
# User Brad Beckmann <brad.beckm...@amd.com>
# Date 1263536246 28800
# Node ID 4bacc747d0a2af5b86d133610118264837282987
# Parent  0cafcd0a9c15571a428675f50a6afe33c0277751
ruby: Added Cache and MemCntrl profiler calls

diff -r 0cafcd0a9c15 -r 4bacc747d0a2 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py     Thu Jan 14 22:17:26 2010 -0800
+++ b/src/mem/slicc/symbols/StateMachine.py     Thu Jan 14 22:17:26 2010 -0800
@@ -236,8 +236,8 @@
     void set_atomic(Address addr);
     void started_writes();
     void clear_atomic();
-    void printStats(ostream& out) const { s_profiler.dumpStats(out); }
-    void clearStats() { s_profiler.clearStats(); }
+    void printStats(ostream& out) const;
+    void clearStats();
 private:
 ''')
 
@@ -593,6 +593,38 @@
     }
 }
 
+void $c_ident::printStats(ostream& out) const {
+''')
+        #
+        # Cache and Memory Controllers have specific profilers associated with
+        # them.  Print out these stats before dumping state transition stats.
+        #
+        for param in self.config_parameters:
+            if param.type_ast.type.ident == "CacheMemory" or \
+                   param.type_ast.type.ident == "MemoryControl":
+                assert(param.pointer)
+                code('    m_${{param.ident}}_ptr->printStats(out);')
+
+        code('''
+    s_profiler.dumpStats(out);
+}
+
+void $c_ident::clearStats() {
+''')
+        #
+        # Cache and Memory Controllers have specific profilers associated with
+        # them.  These stats must be cleared too.
+        #
+        for param in self.config_parameters:
+            if param.type_ast.type.ident == "CacheMemory" or \
+                   param.type_ast.type.ident == "MemoryControl":
+                assert(param.pointer)
+                code('    m_${{param.ident}}_ptr->clearStats();')
+
+        code('''
+    s_profiler.clearStats();
+}
+
 // Actions
 ''')
 

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