> > 1. The first stage of the pipeline should not process the stage when a > drainPending flag is set (or should this be associated specifically > with the fetch logic?) > This sounds good. There is already a "checkSignals" type function in the pipeline stage definition that you may be able to play off of. Maybe defining the drainPending flag in the CPU and then in the first stage's checkSignal function it can check for that drainPending flag and block the stage from processing if that's set.
2. The last stage of the pipeline should check if there are any > entries in the interstage communication structure and call a > signalDrained() routine no entries exist. Again should this be done by > the graduation logic > Hmmm.... What we are basically trying to accomplish here is to signal "drained" when all instructions are out the pipeline. Checking the interstage communication structs can get tricky since they rotate every cycle. Why not just check the CPU's global instruction list of active insts? You could potentially check that list every time an instruction is retired from the CPU (cpu->instDone()???) and then once the list for all threads is empty, the pipeline is officially drained. -- - Korey
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