On Sat, Feb 6, 2010 at 9:08 AM, soumyaroop roy <s...@cse.usf.edu> wrote: > Let me rephrase my last question: > Is there any way that a comparison could be performed between the > checkpoint output by inorder with that output by a simple CPU? Say, if > the number of committed instructions in both are the same when the > checkpoints are dumped, should I expect that the register and memory > state for both CPU's should be identical?
I would expect so, as long as the inorder pipeline is drained and only truly architectural state is checkpointed. > > In any case, what kind of testing strategy should be put in place to > test the correctness of checkpointing apart from just taking > checkpoints for programs/benchmarks, resuming from those checkpoints, > running the programs till completion, and finally verifying the > correctness of the outputs? We've had discussions on this before, though I don't recall all the details of what we've come up with. Certainly the basic idea of taking a checkpoint, restoring from that checkpoint, and then comparing with an execution that didn't stop is a common one. You wouldn't have to run all the way to the end; you could dump statistics and perhaps another checkpoint at a common point further on but not all the way at completion. There is an issue in that the drain operation will perturb the state slightly, so you can't expect the results to be identical unless you either (1) artificially induce a drain without a checkpoint at the same spot in the non-checkpointed execution or (2) do a stats reset at a common point in both simulations after the checkpoint restore. The latter seems a lot simpler to me. Steve _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
