changeset 862a31349d43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=862a31349d43
description:
BaseDynInst: Preserve the faults returned from read and write.
When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls. This patch reinstates them.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/cpu/base_dyn_inst.hh | 4 ++--
diffs (21 lines):
diff -r 4d4903a3e7c5 -r 862a31349d43 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Fri Feb 12 19:53:20 2010 +0000
+++ b/src/cpu/base_dyn_inst.hh Sat Feb 20 20:11:58 2010 +0000
@@ -887,7 +887,7 @@
if (fault == NoFault) {
effAddr = req->getVaddr();
effAddrValid = true;
- cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
+ fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
} else {
// Return a fixed value to keep simulation deterministic even
@@ -933,7 +933,7 @@
if (fault == NoFault) {
effAddr = req->getVaddr();
effAddrValid = true;
- cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
+ fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
}
return fault;
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