changeset 128cce9f92bc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=128cce9f92bc
description:
inorder-stats: add instruction type stats
also, remove inst-req stats as default.good for debugging
but in terms of pure processor stats they aren't useful
diffstat:
src/cpu/inorder/cpu.cc | 49 +++++++++++++++++++++++++++-
src/cpu/inorder/cpu.hh | 9 +++++
src/cpu/inorder/resource.cc | 6 ++-
src/cpu/inorder/resource.hh | 2 +
src/cpu/inorder/resources/agen_unit.cc | 12 +++++++
src/cpu/inorder/resources/agen_unit.hh | 3 +-
src/cpu/inorder/resources/execution_unit.cc | 14 ++-----
src/cpu/inorder/resources/execution_unit.hh | 4 +-
src/cpu/inorder/resources/mult_div_unit.cc | 21 +++++++-----
src/cpu/inorder/resources/mult_div_unit.hh | 8 ++--
src/cpu/inorder/resources/use_def.cc | 23 +++++++++++-
src/cpu/inorder/resources/use_def.hh | 13 +++++++
12 files changed, 132 insertions(+), 32 deletions(-)
diffs (truncated from 395 to 300 lines):
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/cpu.cc Wed Jun 23 18:18:20 2010 -0400
@@ -388,6 +388,34 @@
numCtxtSwitches
.name(name() + ".contextSwitches")
.desc("Number of context switches");
+
+ comLoads
+ .name(name() + ".comLoads")
+ .desc("Number of Load instructions committed");
+
+ comStores
+ .name(name() + ".comStores")
+ .desc("Number of Store instructions committed");
+
+ comBranches
+ .name(name() + ".comBranches")
+ .desc("Number of Branches instructions committed");
+
+ comNops
+ .name(name() + ".comNops")
+ .desc("Number of Nop instructions committed");
+
+ comNonSpec
+ .name(name() + ".comNonSpec")
+ .desc("Number of Non-Speculative instructions committed");
+
+ comInts
+ .name(name() + ".comInts")
+ .desc("Number of Integer instructions committed");
+
+ comFloats
+ .name(name() + ".comFloats")
+ .desc("Number of Floating Point instructions committed");
timesIdled
.name(name() + ".timesIdled")
@@ -436,7 +464,7 @@
.name(name() + ".cpi")
.desc("CPI: Cycles Per Instruction (Per-Thread)")
.precision(6);
- cpi = threadCycles / committedInsts;
+ cpi = numCycles / committedInsts;
smtCpi
.name(name() + ".smt_cpi")
@@ -454,7 +482,7 @@
.name(name() + ".ipc")
.desc("IPC: Instructions Per Cycle (Per-Thread)")
.precision(6);
- ipc = committedInsts / threadCycles;
+ ipc = committedInsts / numCycles;
smtIpc
.name(name() + ".smt_ipc")
@@ -1173,6 +1201,23 @@
smtCommittedInsts[tid]++;
}
+ // Instruction-Mix Stats
+ if (inst->isLoad()) {
+ comLoads++;
+ } else if (inst->isStore()) {
+ comStores++;
+ } else if (inst->isControl()) {
+ comBranches++;
+ } else if (inst->isNop()) {
+ comNops++;
+ } else if (inst->isNonSpeculative()) {
+ comNonSpec++;
+ } else if (inst->isInteger()) {
+ comInts++;
+ } else if (inst->isFloating()) {
+ comFloats++;
+ }
+
// Check for instruction-count-based events.
comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/cpu.hh Wed Jun 23 18:18:20 2010 -0400
@@ -740,6 +740,15 @@
/** Percentage of cycles a stage was active */
Stats::Formula activity;
+ /** Instruction Mix Stats */
+ Stats::Scalar comLoads;
+ Stats::Scalar comStores;
+ Stats::Scalar comBranches;
+ Stats::Scalar comNops;
+ Stats::Scalar comNonSpec;
+ Stats::Scalar comInts;
+ Stats::Scalar comFloats;
+
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/resource.cc Wed Jun 23 18:18:20 2010 -0400
@@ -79,11 +79,13 @@
void
Resource::regStats()
{
+#ifdef DEBUG
instReqsProcessed
.name(name() + ".instReqsProcessed")
.desc("Number of Instructions Requests that completed in "
"this resource.")
.prereq(instReqsProcessed);
+#endif
}
int
@@ -474,8 +476,10 @@
// change slot # to -1, since we check slotNum to see if request is still
valid
slotNum = -1;
-
+
+#ifdef DEBUG
res->instReqsProcessed++;
+#endif
}
ResourceEvent::ResourceEvent()
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/resource.hh Wed Jun 23 18:18:20 2010 -0400
@@ -253,8 +253,10 @@
// DEFAULT RESOURCE STATISTICS
//
/////////////////////////////////////////////////////////////////
+#ifdef DEBUG
/** Number of Instruction Requests the Resource Processes */
Stats::Scalar instReqsProcessed;
+#endif
};
class ResourceEvent : public Event
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/agen_unit.cc
--- a/src/cpu/inorder/resources/agen_unit.cc Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/resources/agen_unit.cc Wed Jun 23 18:18:20 2010 -0400
@@ -37,6 +37,16 @@
{ }
void
+AGENUnit::regStats()
+{
+ agens
+ .name(name() + ".agens")
+ .desc("Number of Address Generations");
+
+ Resource::regStats();
+}
+
+void
AGENUnit::execute(int slot_num)
{
ResourceRequest* agen_req = reqMap[slot_num];
@@ -72,6 +82,8 @@
fatal("%s encountered while calculating address [sn:%i]",
fault->name(), seq_num);
}
+
+ agens++;
} else {
DPRINTF(InOrderAGEN,
"[tid:] Ignoring non-memory instruction [sn:%i]\n",
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/agen_unit.hh
--- a/src/cpu/inorder/resources/agen_unit.hh Wed Jun 23 18:15:23 2010 -0400
+++ b/src/cpu/inorder/resources/agen_unit.hh Wed Jun 23 18:18:20 2010 -0400
@@ -56,9 +56,10 @@
};
virtual void execute(int slot_num);
+ void regStats();
protected:
- /** @todo: Add Resource Stats Here */
+ Stats::Scalar agens;
};
#endif //__CPU_INORDER_DECODE_UNIT_HH__
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/execution_unit.cc
--- a/src/cpu/inorder/resources/execution_unit.cc Wed Jun 23 18:15:23
2010 -0400
+++ b/src/cpu/inorder/resources/execution_unit.cc Wed Jun 23 18:18:20
2010 -0400
@@ -56,14 +56,9 @@
lastExecuteCycle = curTick;
- cyclesExecuted
- .name(name() + ".cyclesExecuted")
- .desc("Number of Cycles Execution Unit was used.");
-
- utilization
- .name(name() + ".utilization")
- .desc("Utilization of Execution Unit (cycles / totalCycles).");
- utilization = cyclesExecuted / cpu->numCycles;
+ executions
+ .name(name() + ".executions")
+ .desc("Number of Instructions Executed.");
Resource::regStats();
}
@@ -88,7 +83,6 @@
{
if (curTick != lastExecuteCycle) {
lastExecuteCycle = curTick;
- cyclesExecuted++;
}
@@ -97,6 +91,7 @@
} else if (inst->isControl()) {
// Evaluate Branch
fault = inst->execute();
+ executions++;
inst->setExecuted();
@@ -190,6 +185,7 @@
} else {
// Regular ALU instruction
fault = inst->execute();
+ executions++;
if (fault == NoFault) {
inst->setExecuted();
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/execution_unit.hh
--- a/src/cpu/inorder/resources/execution_unit.hh Wed Jun 23 18:15:23
2010 -0400
+++ b/src/cpu/inorder/resources/execution_unit.hh Wed Jun 23 18:18:20
2010 -0400
@@ -71,10 +71,8 @@
Stats::Scalar predictedTakenIncorrect;
Stats::Scalar predictedNotTakenIncorrect;
- Stats::Scalar cyclesExecuted;
+ Stats::Scalar executions;
Tick lastExecuteCycle;
-
- Stats::Formula utilization;
};
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/mult_div_unit.cc
--- a/src/cpu/inorder/resources/mult_div_unit.cc Wed Jun 23 18:15:23
2010 -0400
+++ b/src/cpu/inorder/resources/mult_div_unit.cc Wed Jun 23 18:18:20
2010 -0400
@@ -53,13 +53,13 @@
void
MultDivUnit::regStats()
{
- multInstReqsProcessed
- .name(name() + ".multInstReqsProcessed")
- .desc("Number of Multiply Requests Processed.");
+ multiplies
+ .name(name() + ".multiplies")
+ .desc("Number of Multipy Operations Executed");
- divInstReqsProcessed
- .name(name() + ".divInstReqsProcessed")
- .desc("Number of Divide Requests Processed.");
+ divides
+ .name(name() + ".divides")
+ .desc("Number of Divide Operations Executed");
Resource::regStats();
}
@@ -209,7 +209,6 @@
if (inst->opClass() == IntMultOp) {
scheduleEvent(slot_num, multLatency);
- multInstReqsProcessed++;
} else if (inst->opClass() == IntDivOp) {
int op_size = getDivOpSize(inst);
@@ -233,8 +232,6 @@
}
lastDivSize = op_size;
-
- divInstReqsProcessed++;
}
// Allow to pass through to next stage while
@@ -283,6 +280,12 @@
fault = inst->execute();
+ if (inst->opClass() == IntMultOp) {
+ multiplies++;
+ } else if (inst->opClass() == IntDivOp) {
+ divides++;
+ }
+
if (fault == NoFault) {
inst->setExecuted();
mult_div_req->setCompleted();
diff -r e3311623d9f0 -r 128cce9f92bc src/cpu/inorder/resources/mult_div_unit.hh
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