changeset 97bb8e7068d3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=97bb8e7068d3
description:
inorder: enforce 78-character rule
diffstat:
src/cpu/inorder/cpu.cc | 19 +-
src/cpu/inorder/cpu.hh | 4 +-
src/cpu/inorder/inorder_dyn_inst.cc | 19 +-
src/cpu/inorder/inorder_dyn_inst.hh | 11 +-
src/cpu/inorder/pipeline_stage.cc | 41 +++--
src/cpu/inorder/reg_dep_map.cc | 21 +-
src/cpu/inorder/reg_dep_map.hh | 19 ++-
src/cpu/inorder/resource.cc | 14 +-
src/cpu/inorder/resource_pool.cc | 42 ++++--
src/cpu/inorder/resources/agen_unit.cc | 3 +-
src/cpu/inorder/resources/agen_unit.hh | 2 +-
src/cpu/inorder/resources/bpred_unit.cc | 58 +++++----
src/cpu/inorder/resources/bpred_unit.hh | 5 +-
src/cpu/inorder/resources/branch_predictor.cc | 31 ++--
src/cpu/inorder/resources/cache_unit.cc | 157 ++++++++++++++-----------
src/cpu/inorder/resources/cache_unit.hh | 3 +-
src/cpu/inorder/resources/decode_unit.cc | 3 +-
src/cpu/inorder/resources/execution_unit.cc | 69 +++++++----
src/cpu/inorder/resources/fetch_seq_unit.cc | 63 ++++++----
src/cpu/inorder/resources/graduation_unit.cc | 13 +-
src/cpu/inorder/resources/graduation_unit.hh | 3 +-
src/cpu/inorder/resources/inst_buffer.cc | 65 ++++++----
src/cpu/inorder/resources/inst_buffer.hh | 2 +-
src/cpu/inorder/resources/mem_dep_unit.hh | 4 +-
src/cpu/inorder/resources/mult_div_unit.cc | 35 +++--
src/cpu/inorder/resources/mult_div_unit.hh | 3 +-
src/cpu/inorder/resources/use_def.cc | 3 +-
src/cpu/inorder/resources/use_def.hh | 2 +-
src/cpu/inorder/thread_context.cc | 9 +-
src/cpu/inorder/thread_context.hh | 6 +-
30 files changed, 435 insertions(+), 294 deletions(-)
diffs (truncated from 1859 to 300 lines):
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/cpu.cc Thu Jun 24 15:34:12 2010 -0400
@@ -158,9 +158,11 @@
InOrderCPU::CPUEvent::scheduleEvent(int delay)
{
if (squashed())
- mainEventQueue.reschedule(this, cpu->nextCycle(curTick +
cpu->ticks(delay)));
+ mainEventQueue.reschedule(this, cpu->nextCycle(curTick +
+ cpu->ticks(delay)));
else if (!scheduled())
- mainEventQueue.schedule(this, cpu->nextCycle(curTick +
cpu->ticks(delay)));
+ mainEventQueue.schedule(this, cpu->nextCycle(curTick +
+ cpu->ticks(delay)));
}
void
@@ -674,7 +676,8 @@
void
-InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID
tid)
+InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
+ ThreadID tid)
{
DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
@@ -965,7 +968,8 @@
void
InOrderCPU::suspendThread(ThreadID tid)
{
- DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
tid);
+ DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
+ tid);
deactivateThread(tid);
suspendedThreads.push_back(tid);
thread[tid]->lastSuspend = curTick;
@@ -1323,8 +1327,8 @@
(*instIt)->setRemoveList();
removeList.push(instIt);
} else {
- DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC
%#x "
- "[sn:%lli], already on remove list\n",
+ DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
+ " PC %#x [sn:%lli], already on remove list\n",
(*instIt)->threadNumber, (*instIt)->readPC(),
(*instIt)->seqNum);
}
@@ -1387,7 +1391,8 @@
res_req->inst->seqNum,
res_req->getStageNum(),
res_req->res->name(),
- (res_req->isCompleted()) ? res_req->getComplSlot() :
res_req->getSlot(),
+ (res_req->isCompleted()) ?
+ res_req->getComplSlot() : res_req->getSlot(),
res_req->isCompleted());
reqRemoveList.pop();
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/cpu.hh Thu Jun 24 15:34:12 2010 -0400
@@ -731,7 +731,9 @@
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
- /** Stat for total number of cycles the CPU spends descheduled or no
stages active. */
+ /** Stat for total number of cycles the CPU spends descheduled or no
+ * stages active.
+ */
Stats::Scalar idleCycles;
/** Stat for total number of cycles the CPU is active. */
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Thu Jun 24 15:34:12 2010 -0400
@@ -172,8 +172,8 @@
- DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created.
(active insts: %i)\n",
- threadNumber, seqNum, instcount);
+ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
+ " (active insts: %i)\n", threadNumber, seqNum, instcount);
}
void
@@ -209,8 +209,8 @@
deleteStages();
- DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction
destroyed. (active insts: %i)\n",
- threadNumber, seqNum, instcount);
+ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed"
+ " (active insts: %i)\n", threadNumber, seqNum, instcount);
}
void
@@ -387,8 +387,8 @@
while(list_it != list_end) {
if((*list_it)->getResIdx() == req->getResIdx() &&
(*list_it)->getSlot() == req->getSlot()) {
- DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request to
%s.\n",
- threadNumber, seqNum, req->res->name());
+ DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request "
+ "to %s.\n", threadNumber, seqNum, req->res->name());
reqList.erase(list_it);
return;
}
@@ -402,8 +402,8 @@
void
InOrderDynInst::setIntSrc(int idx, uint64_t val)
{
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set to
%#x.\n",
- threadNumber, seqNum, idx, val);
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
+ "to %#x.\n", threadNumber, seqNum, idx, val);
instSrc[idx].integer = val;
}
@@ -757,7 +757,8 @@
return hash;
}
-typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
MyHashFunc>
+typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
+ MyHashFunc>
my_hash_t;
my_hash_t thishash;
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Thu Jun 24 15:34:12 2010 -0400
@@ -141,7 +141,7 @@
InstSeqNum bdelaySeqNum;
enum Status {
- RegDepMapEntry, /// Instruction has been entered onto the
RegDepMap
+ RegDepMapEntry, /// Instruction is entered onto the RegDepMap
IqEntry, /// Instruction is in the IQ
RobEntry, /// Instruction is in the ROB
LsqEntry, /// Instruction is in the LSQ
@@ -648,8 +648,8 @@
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
- /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
Access
- * Only valid for memory operations.
+ /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
+ * Access Only valid for memory operations.
*/
Fault initiateAcc();
@@ -685,7 +685,7 @@
/** Returns the effective address. */
const Addr &getEA() const { return instEffAddr; }
- /** Returns whether or not the eff. addr. calculation has been completed.
*/
+ /** Returns whether or not the eff. addr. calculation has been completed.*/
bool doneEACalc() { return eaCalcDone; }
/** Returns whether or not the eff. addr. source registers are ready.
@@ -895,7 +895,8 @@
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
- void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const
MiscReg &val);
+ void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
+ const MiscReg &val);
virtual uint64_t readRegOtherThread(unsigned idx,
ThreadID tid = InvalidThreadID);
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/pipeline_stage.cc Thu Jun 24 15:34:12 2010 -0400
@@ -235,17 +235,20 @@
{
for (int st_num = 0; st_num < NumStages; st_num++) {
if (stalls[tid].stage[st_num] == true) {
- DPRINTF(InOrderStage, "Removing stall from stage %i.\n", st_num);
+ DPRINTF(InOrderStage, "Removing stall from stage %i.\n",
+ st_num);
stalls[tid].stage[st_num] = false;
}
if (toPrevStages->stageBlock[st_num][tid] == true) {
- DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
+ st_num);
toPrevStages->stageBlock[st_num][tid] = false;
}
if (fromNextStages->stageBlock[st_num][tid] == true) {
- DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
+ st_num);
fromNextStages->stageBlock[st_num][tid] = false;
}
}
@@ -568,15 +571,15 @@
} else {
DynInstPtr inst = switchedOutBuffer[tid];
- DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into
"
- "stage skidBuffer %i\n", tid, inst->seqNum,
+ DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into"
+ " stage skidBuffer %i\n", tid, inst->seqNum,
inst->readPC(), inst->threadNumber);
// Make instruction available for pipeline processing
skidBuffer[tid].push(inst);
- // Update PC so that we start fetching after this instruction to
prevent
- // "double"-execution of instructions
+ // Update PC so that we start fetching after this instruction to
+ // prevent "double"-execution of instructions
cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
ResourcePool::UpdateAfterContextSwitch,
inst, 0, 0, tid);
@@ -988,10 +991,11 @@
if (req->isMemStall() &&
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
// Save Stalling Instruction
- DPRINTF(ThreadModel, "[tid:%i] [sn:%i] Detected cache
miss.\n", tid, inst->seqNum);
+ DPRINTF(ThreadModel, "[tid:%i] [sn:%i] Detected cache "
+ "miss.\n", tid, inst->seqNum);
- DPRINTF(InOrderStage, "Inserting [tid:%i][sn:%i] into
switch out buffer.\n",
- tid, inst->seqNum);
+ DPRINTF(InOrderStage, "Inserting [tid:%i][sn:%i] into "
+ "switch out buffer.\n", tid, inst->seqNum);
switchedOutBuffer[tid] = inst;
switchedOutValid[tid] = true;
@@ -1004,26 +1008,27 @@
// Switch On Cache Miss
//=====================
// Suspend Thread at end of cycle
- DPRINTF(ThreadModel, "Suspending [tid:%i] due to cache
miss.\n", tid);
+ DPRINTF(ThreadModel, "Suspending [tid:%i] due to cache "
+ "miss.\n", tid);
cpu->suspendContext(tid);
// Activate Next Ready Thread at end of cycle
- DPRINTF(ThreadModel, "Attempting to activate next ready
thread due to"
- " cache miss.\n");
+ DPRINTF(ThreadModel, "Attempting to activate next ready "
+ "thread due to cache miss.\n");
cpu->activateNextReadyContext();
}
// Mark request for deletion
// if it isnt currently being used by a resource
if (!req->hasSlot()) {
- DPRINTF(InOrderStage, "[sn:%i] Deleting Request, has no
slot in resource.\n",
- inst->seqNum);
+ DPRINTF(InOrderStage, "[sn:%i] Deleting Request, has no "
+ "slot in resource.\n", inst->seqNum);
cpu->reqRemoveList.push(req);
} else {
- DPRINTF(InOrderStage, "[sn:%i] Ignoring Request Deletion,
in resource [slot:%i].\n",
- inst->seqNum, req->getSlot());
- //req = cpu->dummyReq[tid];
+ DPRINTF(InOrderStage, "[sn:%i] Ignoring Request Deletion, "
+ "in resource [slot:%i].\n", inst->seqNum,
+ req->getSlot());
}
diff -r 207e034f6bb2 -r 97bb8e7068d3 src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Thu Jun 24 13:58:27 2010 -0400
+++ b/src/cpu/inorder/reg_dep_map.cc Thu Jun 24 15:34:12 2010 -0400
@@ -154,8 +154,9 @@
if (inst->seqNum <= (*list_it)->seqNum) {
return true;
} else {
- DPRINTF(RegDepMap, "[sn:%i] Can't read from RegFile, [sn:%i] has not
written"
- " it's value back yet.\n", inst->seqNum, (*list_it)->seqNum);
+ DPRINTF(RegDepMap, "[sn:%i] Can't read from RegFile, [sn:%i] has "
+ "not written it's value back yet.\n",
+ inst->seqNum, (*list_it)->seqNum);
return false;
}
}
@@ -184,13 +185,14 @@
return forward_inst;
} else {
if (!forward_inst->isExecuted()) {
- DPRINTF(RegDepMap, "[sn:%i] Can't get value through
forwarding, "
- " [sn:%i] has not been executed yet.\n",
+ DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
+ "forwarding, [sn:%i] has not been executed yet.\n",
inst->seqNum, forward_inst->seqNum);
} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick) {
- DPRINTF(RegDepMap, "[sn:%i] Can't get value through
forwarding, "
- " [sn:%i] executed on tick:%i.\n",
- inst->seqNum, forward_inst->seqNum,
forward_inst->readResultTime(dest_reg_idx));
+ DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
+ "forwarding, [sn:%i] executed on tick:%i.\n",
+ inst->seqNum, forward_inst->seqNum,
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
