changeset 69d054e9e61c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=69d054e9e61c
description:
inorder: cleanup virtual functions
remove the annotation 'virtual' from function declaration that isnt
being derived from
diffstat:
src/cpu/inorder/cpu.hh | 6 +-
src/cpu/inorder/pipeline_stage.hh | 34 +++---
src/cpu/inorder/pipeline_traits.hh | 2 -
src/cpu/inorder/resource.hh | 4 +-
src/cpu/inorder/resource_pool.hh | 2 +-
src/cpu/inorder/resources/agen_unit.hh | 1 -
src/cpu/inorder/resources/branch_predictor.hh | 8 +-
src/cpu/inorder/resources/cache_unit.hh | 16 +-
src/cpu/inorder/resources/decode_unit.hh | 3 +-
src/cpu/inorder/resources/execution_unit.hh | 4 +-
src/cpu/inorder/resources/fetch_seq_unit.hh | 18 +-
src/cpu/inorder/resources/graduation_unit.hh | 3 +-
src/cpu/inorder/resources/inst_buffer.hh | 15 +-
src/cpu/inorder/resources/mult_div_unit.hh | 16 +-
src/cpu/inorder/resources/use_def.hh | 9 +-
src/cpu/inorder/thread_context.hh | 130 +++++++++++++-------------
16 files changed, 131 insertions(+), 140 deletions(-)
diffs (truncated from 745 to 300 lines):
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/cpu.hh Thu Jun 24 15:34:19 2010 -0400
@@ -222,10 +222,10 @@
vpe = 0;
}
- /** Processes a resource event. */
- virtual void process();
+ /** Processes a CPU event. */
+ void process();
- /** Returns the description of the resource event. */
+ /** Returns the description of the CPU event. */
const char *description();
/** Schedule Event */
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/pipeline_stage.hh Thu Jun 24 15:34:19 2010 -0400
@@ -106,9 +106,7 @@
void regStats();
/** Sets CPU pointer. */
- virtual void setCPU(InOrderCPU *cpu_ptr);
-
- virtual void scheduleStageStart(int delay, ThreadID tid) { }
+ void setCPU(InOrderCPU *cpu_ptr);
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@@ -145,7 +143,7 @@
/** Ticks stage, processing all input signals and executing as many
* instructions as possible.
*/
- virtual void tick();
+ void tick();
/** Set a resource stall in the pipeline-stage */
void setResStall(ResReqPtr res_req, ThreadID tid);
@@ -154,7 +152,7 @@
void unsetResStall(ResReqPtr res_req, ThreadID tid);
/** Remove all stall signals for a particular thread; */
- virtual void removeStalls(ThreadID tid);
+ void removeStalls(ThreadID tid);
/** Is there room in the stage buffer? */
int stageBufferAvail();
@@ -168,7 +166,7 @@
* change (ie switching from from blocking to unblocking).
* @param tid Thread id to stage instructions from.
*/
- virtual void processThread(bool &status_change, ThreadID tid);
+ void processThread(bool &status_change, ThreadID tid);
/** Processes instructions from fetch and passes them on to rename.
* Decoding of instructions actually happens when they are created in
@@ -178,13 +176,13 @@
virtual void processInsts(ThreadID tid);
/** Process all resources on an instruction's resource schedule */
- virtual bool processInstSchedule(DynInstPtr inst, int &reqs_processed);
+ bool processInstSchedule(DynInstPtr inst, int &reqs_processed);
/** Is there room in the next stage buffer for this instruction? */
- virtual bool canSendInstToStage(unsigned stage_num);
+ bool canSendInstToStage(unsigned stage_num);
/** Send an instruction to the next stage buffer */
- virtual bool sendInstToNextStage(DynInstPtr inst);
+ bool sendInstToNextStage(DynInstPtr inst);
/** Inserts a thread's instructions into the skid buffer, to be staged
* once stage unblocks.
@@ -198,7 +196,7 @@
bool skidsEmpty();
/** Updates overall stage status based on all of the threads' statuses. */
- virtual void updateStatus();
+ void updateStatus();
/** Separates instructions from fetch into individual lists of instructions
* sorted by thread.
@@ -206,13 +204,13 @@
void sortInsts();
/** Reads all stall signals from the backwards communication timebuffer. */
- virtual void readStallSignals(ThreadID tid);
+ void readStallSignals(ThreadID tid);
/** Checks all input signals and updates stage's status appropriately. */
- virtual bool checkSignalsAndUpdate(ThreadID tid);
+ bool checkSignalsAndUpdate(ThreadID tid);
/** Checks all stall signals, and returns if any are true. */
- virtual bool checkStall(ThreadID tid) const;
+ bool checkStall(ThreadID tid) const;
/** Returns if there any instructions from the previous stage
* on this cycle.
@@ -223,7 +221,7 @@
* become blocked.
* @return Returns true if there is a status change.
*/
- virtual bool block(ThreadID tid);
+ bool block(ThreadID tid);
void blockDueToBuffer(ThreadID tid);
@@ -231,21 +229,21 @@
* signals back that stage has unblocked.
* @return Returns true if there is a status change.
*/
- virtual bool unblock(ThreadID tid);
+ bool unblock(ThreadID tid);
public:
- virtual void activateThread(ThreadID tid);
+ void activateThread(ThreadID tid);
/** Squashes if there is a PC-relative branch that was predicted
* incorrectly. Sends squash information back to fetch.
*/
- virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
+ void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
virtual void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid);
/** Squash instructions from stage buffer */
- virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
+ void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
/** Squashes due to commit signalling a squash. Changes status to
* squashing and clears block/unblock signals as needed.
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/pipeline_traits.hh
--- a/src/cpu/inorder/pipeline_traits.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/pipeline_traits.hh Thu Jun 24 15:34:19 2010 -0400
@@ -95,8 +95,6 @@
idx(_idx), priority(_priority)
{ }
- virtual ~ScheduleEntry(){}
-
// Stage number to perform this service.
int stageNum;
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/resource.hh Thu Jun 24 15:34:19 2010 -0400
@@ -132,7 +132,7 @@
unsigned cmd);
/** Schedule Execution of This Resource For A Given Slot*/
- virtual void scheduleExecution(int slot_idx);
+ void scheduleExecution(int slot_idx);
/** Execute the function of this resource. The Default is action
* is to do nothing. More specific models will derive from this
@@ -195,7 +195,7 @@
virtual ResReqPtr findRequest(DynInstPtr inst);
/** */
- virtual void rejectRequest(DynInstPtr inst);
+ void rejectRequest(DynInstPtr inst);
/** Request a Resource again. Some resources have to special process this
* in subsequent accesses.
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/resource_pool.hh Thu Jun 24 15:34:19 2010 -0400
@@ -108,7 +108,7 @@
}
/** Processes a resource event. */
- virtual void process();
+ void process();
/** Returns the description of the resource event. */
const char *description();
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resources/agen_unit.hh
--- a/src/cpu/inorder/resources/agen_unit.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/resources/agen_unit.hh Thu Jun 24 15:34:19 2010 -0400
@@ -49,7 +49,6 @@
public:
AGENUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
- virtual ~AGENUnit() {}
enum Command {
GenerateAddr
diff -r 97bb8e7068d3 -r 69d054e9e61c
src/cpu/inorder/resources/branch_predictor.hh
--- a/src/cpu/inorder/resources/branch_predictor.hh Thu Jun 24 15:34:12
2010 -0400
+++ b/src/cpu/inorder/resources/branch_predictor.hh Thu Jun 24 15:34:19
2010 -0400
@@ -56,14 +56,14 @@
BranchPredictor(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
- virtual void regStats();
+ void regStats();
- virtual void execute(int slot_num);
+ void execute(int slot_num);
- virtual void squash(DynInstPtr inst, int stage_num,
+ void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
- virtual void instGraduated(InstSeqNum seq_num, ThreadID tid);
+ void instGraduated(InstSeqNum seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Thu Jun 24 15:34:19 2010 -0400
@@ -101,30 +101,30 @@
protected:
/** Atomic version of receive. Panics. */
- virtual Tick recvAtomic(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt);
/** Functional version of receive. Panics. */
- virtual void recvFunctional(PacketPtr pkt);
+ void recvFunctional(PacketPtr pkt);
/** Receives status change. Other than range changing, panics. */
- virtual void recvStatusChange(Status status);
+ void recvStatusChange(Status status);
/** Returns the address ranges of this device. */
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
- virtual bool recvTiming(PacketPtr pkt);
+ bool recvTiming(PacketPtr pkt);
/** Handles doing a retry of a failed fetch. */
- virtual void recvRetry();
+ void recvRetry();
};
void init();
- virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
+ ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num,
unsigned cmd);
@@ -238,7 +238,7 @@
virtual ~CacheUnitEvent() {}
/** Processes a resource event. */
- virtual void process();
+ void process();
};
class CacheRequest : public ResourceRequest
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resources/decode_unit.hh
--- a/src/cpu/inorder/resources/decode_unit.hh Thu Jun 24 15:34:12 2010 -0400
+++ b/src/cpu/inorder/resources/decode_unit.hh Thu Jun 24 15:34:19 2010 -0400
@@ -49,13 +49,12 @@
public:
DecodeUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
- virtual ~DecodeUnit() {}
enum Command {
DecodeInst
};
- virtual void execute(int slot_num);
+ void execute(int slot_num);
void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid);
diff -r 97bb8e7068d3 -r 69d054e9e61c src/cpu/inorder/resources/execution_unit.hh
--- a/src/cpu/inorder/resources/execution_unit.hh Thu Jun 24 15:34:12
2010 -0400
+++ b/src/cpu/inorder/resources/execution_unit.hh Thu Jun 24 15:34:19
2010 -0400
@@ -54,13 +54,13 @@
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
public:
- virtual void regStats();
+ void regStats();
/** Execute the function of this resource. The Default is action
* is to do nothing. More specific models will derive from this
* class and define their own execute function.
*/
- virtual void execute(int slot_num);
+ void execute(int slot_num);
protected:
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