> On 2010-07-10 08:57:34, Steve Reinhardt wrote: > > I'm curious about the overall need for this... is there really a situation > > where it matters? If there's some path that's not appropriately > > setting/checking/ignoring the whenReady field I'd rather fix that than add > > this feature. > > Timothy Jones wrote: > I added this in mainly because the SMARTS reference implementation has it > - it's called after functional warming before starting warming of the O3CPU. > If the functional warming is long enough then it shouldn't be needed. If > it's quite short then the whenReady field of blocks accessed in the previous > measurement phase could be later than the start tick of the next detailed > warming period. In that case, they would also be later than blocks accessed > during functional warming, which would be wrong. I can try to get an example > of when this could happen if you like?
No, I get this now... I think we ignore the latencies returned in TimingSimpleCPU, and I doubt whenReady is used much in timing mode, so perhaps some day we should just get rid of whenReady. But for now your solution makes sense. - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/53/#review66 ----------------------------------------------------------- On 2010-07-09 18:16:18, Timothy Jones wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/53/ > ----------------------------------------------------------- > > (Updated 2010-07-09 18:16:18) > > > Review request for Default. > > > Summary > ------- > > Cache: Provide a function to mark caches as ready from python. > > > Diffs > ----- > > src/mem/cache/BaseCache.py 249f174e6f37 > src/mem/cache/base.hh 249f174e6f37 > src/mem/cache/cache.hh 249f174e6f37 > src/mem/cache/cache_impl.hh 249f174e6f37 > src/mem/cache/tags/base.hh 249f174e6f37 > src/mem/cache/tags/lru.hh 249f174e6f37 > src/mem/cache/tags/lru.cc 249f174e6f37 > src/python/swig/sim_object.i 249f174e6f37 > src/sim/sim_object.hh 249f174e6f37 > src/sim/sim_object.cc 249f174e6f37 > > Diff: http://reviews.m5sim.org/r/53/diff > > > Testing > ------- > > > Thanks, > > Timothy > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
