On Tue, Jul 13, 2010 at 10:35 AM, Korey Sewell <ksew...@umich.edu> wrote: > >> Thoughts? Volunteers? :-) > > I had thoughts on similar tasks where you would need to do some editing on a > memory request > after it's been sent to the CPU. > > I wouldnt mind a shim object so to speak, but what about deriving a new > class of port to handle this? > There is already a "translating" port that kind of adds some functionality > over just sending the access. > Could there not be a "shim-port" or "aligning" port that automatically adds > this functionality?
Yea, these ports are pretty close to what I had in mind; the readBlob/writeBlob methods kind of do this already only just for functional accesses. Since the shim will have to maintain some state for timing accesses it might make sense to make it a separate object (perhaps even a SimObject) rather than try and embed it all in a class derived from Port. Both approaches are worth considering. > This might also serve as part of the solution to people asking for caches > with different blocksizes as a downstream > request that is going from larger-to-smaller blocksize could use that > "aligning" port to break up the request into however > many chunks are necessary (i guess it wouldnt be purely aligning in the > literal sense but i couldnt think of a more applicable word!). This would be one way to do it... it may or may not be the best way depending on what your goals are. Steve _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
